Input stage resistant against high voltage swings
View Patent ↗An input stage includes a signal input (IN) for receiving an input signal s(t) and a digital input stage ( 15 ) designed for operation at a supply voltage (VDD). The input stage ( 15 ) includes CMOS transistors, which are sensitive to voltages across transistor nodes going beyond a voltage limit (V max ) and an input (IINV). Voltage limiting circuitry (B) is arranged between the signal input (IN) and the input (IINV). The voltage limiting circuitry (B) includes an input switch (ns) controllable by the state of the input signal s(t), and limit voltages at the input (IINV) to the supply voltage (VDD). In addition, over-voltage protection (A) is provided between the signal input (IN) and the supply voltage (VDD). The circuitry for over-voltage protection (A) includes at least one active circuit element arranged so as to mimic part of a zener function.
1. A circuit comprising:
signal input (IN) for receiving an input signal (s(t)),
a digital input stage ( 15 ) being designed for operation at a supply voltage (VDD), the digital input stage ( 15 ) comprising:
CMOS transistors sensitive to voltages across transistor nodes going beyond a voltage limit (V max )
an input (IINV),
voltage limiting means (B) being arranged between the signal input (IN) and the input (IINV) for limiting voltages at the input (IINV) to the supply voltage (VDD), the voltage limiting means (B) comprising:
an input switch (ns) being controllable by the state of the input signal (s(t)),
means for over-voltage protection (A) being situated between the signal input (IN) and the supply voltage (VDD), the means for over-voltage protection (A) comprising at least one active circuit element which functions so as to mimic at least a breakdown part of a zener function, and
speed boost means (C) having at least one capacitive element (Cb) speeding up the turn-on/turn-off behavior of the input switch (ns).
2. The circuit of claim 1 , wherein the element is a transistor being arranged such that during normal operation the transistor does not enter conductive state.
3. The circuit of claim 1 or 2 , wherein the transistor of the means for over-voltage protection (A) includes at least one of an n-channel MOS transistor (nz 1 , nz 2 , nz 3 ), a p-channel MOS transistor, and a bipolar transistor, and the means for over-voltage protection (A) further comprises a resistor (Rz).
4. The circuit of claim 1 or 2 , further comprising a current limiting resistor (R 1 ) being situated between the signal input (IN) and an input node (IN 0 ), and an input protection diode (D 1 ) being situated between the input node (IN 0 ) and ground.
5. The circuit of claim 1 or 2 , further comprising means (D) for protection against static currents.
6. The circuit of claim 5 , wherein the means (D) for protection against static currents provide for a positive feedback pulling the input (IINV) up to the supply voltage (VDD) in order to prevent the static currents from flowing through part (pi 1 , ni 1 ) of the input stage ( 15 ).
7. The circuit of claim 5 , wherein the means (D) for protection against static currents comprise a p-type CMOS transistor (pp 2 ) serving as keeper transistor.
8. The circuit of claim 1 , wherein the charging of the capacitive element (Cb) depends on the state of a signal derived, from the input signal (s(t)).
9. The circuit of claim 8 , wherein the capacitive element (Cb) is charged to the supply voltage (Vdd) if the input signal (s(t)) is low.
10. The circuit of claim 1 or 2 , wherein the input switch is an n-channel MOS transistor (ns).
11. The circuit of claim 1 or 2 , wherein the means for over-voltage protection (A) absorb destructive voltages when the supply voltage (VDD) is zero.
12. Circuit according to claim 1 or 2 being made using a submicron fabrication process, preferably a deep submicron fabrication process.
13. A circuit comprising:
signal input (IN) for receiving an input signal (s(t)),
a digital input stage ( 15 ) being designed for operation at a supply voltage (VDD), the digital input stage ( 15 ) comprising:
CMOS transistors sensitive to voltages across transistor nodes going beyond a voltage limit (Vmax),
an input (IINV),
voltage limiting means (B) being arranged between the signal input (IN) and the input (IINV) for limiting voltages at the input (IINV) to the supply voltage (VDD), the voltage limiting means (B) comprising:
an input switch (ns) being controllable by the state of the input signal (s(t)),
means for over-voltage protection (A) being situated between the signal input (IN) and the supply voltage (VDD), the means for over-voltage protection (A) comprising at least one active circuit element which functions so as to mimic at least a breakdown part of a zener function, wherein the input switch is an n-channel MOS transistor (ns), and wherein the voltage limiting means (B) further comprise a p-channel MOS transistor (pp 1 ) for controlling the voltage at the gate node (GNS) of the n-channel MOS transistor (ns).