IP Library Granted Patent US 7,315,332
Granted Patent B2
US 7,315,332 · App. 10/513,482 · Granted Jan 1, 2008

Video and text display with reduced text flicker

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Quick Facts
Patent No.
US 7,315,332
App. No.
10/513,482
Granted
Jan 1, 2008
Kind
B2
Abstract

A display apparatus comprises a signal converter (SC) which converts input text information (IT) and interlaced input video information (IV) with a number of video lines (Li) in a video field (Fi) into a display signal (DS) which comprises display text (Ti) and display video (Vi). An addressing circuit (AD) addresses a display screen (DSC) of the display apparatus in successive non-interlaced display fields (Fi) which have a duration substantially equal to the video field (Fi) and a number of display lines (DLi) which is substantially twice the number of video lines (Li). The signal converter (SC) has an output to supply the display signal (DS) in which the display video (Vi) is present on odd or even display lines (DLi) only, in respective successive display fields (Fi), and in which the display text (Ti) is present on same display lines (DLi) of the successive display fields (Fi).

Claims (17)

1. A display apparatus comprising:

a signal converter for converting input text information and interlaced input video information having a number of video lines in a video field into a display signal (DS) comprising display text and display video, and

addressing means for addressing a display screen of the display apparatus in successive non-interlaced display fields having a substantially same duration as the video field and a number of display lines being substantially twice the number of video lines,

wherein the signal converter has an output for supplying the display signal in which the display video is present on odd or even display lines only in respective successive display fields, and in which the display text is present on same display lines of the successive display fields.

2. A display apparatus as claimed in claim 1 , wherein the signal converter comprises a memory and a clock generator for supplying a write clock to the memory to store said input video information in the memory, and for supplying a read clock to the memory to read the display video from the memory, wherein the read clock has a repetition frequency which is at least two times higher than a repetition frequency of the write clock.

3. A display apparatus as claimed in claim 2 , wherein the signal converter further comprises a controller for controlling the clock generator to supply the read clock only during odd display lines of a predetermined display field and only during even lines of a successive display field.

4. A display apparatus as claimed in claim 1 , wherein the display apparatus comprises a text generator for supplying the input text information being the display text, and the signal converter comprises a controller for controlling the text generator to supply the display text on same lines of said successive display fields.

5. A display apparatus as claimed in claim 4 , wherein the text generator has an input for receiving timing information from the controller to supply the display text on either the odd or the even lines of the display fields.

6. A display apparatus as claimed in claim 4 , wherein the text generator has an input for receiving timing information from the controller to supply the display text on substantially all the lines of the display fields.

7. A display apparatus as claimed in claim 1 , wherein the display apparatus further comprises means for supplying a black-level to the display lines or part of the display lines on which no display video or no display text is displayed.

8. A display apparatus as claimed in claim 2 , wherein the display apparatus comprises a text generator for supplying the input text information being the display text, and the signal converter comprises a controller for controlling the text generator to supply the display text on same lines of said successive display fields, wherein the repetition frequency of the read clock is four times the repetition frequency of the write clock, and wherein the controller is adapted for controlling the memory to supply the display video on either a left or right halve of the display screen, and for controlling the text generator to supply the display text on a remaining halve of the display screen.

9. A display apparatus as claimed in claim 2 , wherein the memory comprises two line memories for storing data of a predetermined one of the video lines in one of the two line memories, and reading the display video of a preceding video line from the other line memory.

10. A signal converter for converting input text information and interlaced input video information having a number of video lines in a video field into a display signal suitable for display on a display screen of a display apparatus being addressed in successive non-interlaced display fields having a substantially same duration as the video field and a number of display lines being substantially twice the number of video lines, the display signal comprising display text and display video,

the signal converter having an output for supplying the display signal comprising, in successive display fields, the display video alternatively on odd or even display lines only, and the display text on same display lines of said successive display fields.

11. A method of converting input text information and interlaced input video information having a number of video lines in a video field into a display signal comprising display text and display video, the method comprising

addressing a display screen of a display apparatus in successive non-interlaced display fields having a substantially same duration as the video field and a number of display lines being substantially twice the number of video lines,

supplying, in successive display fields, the display video alternatively on odd or even display lines only, and for supplying the display text on same display lines of said successive display fields.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: TRIDENT MICROSYSTEMS, INC.; TRIDENT MICROSYSTEMS (FAR EAST) LTD.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 028153/0440 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: NXP
To: NXP HOLDING 1 B.V.
Reel/Frame 023928/0489 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: TRIDENT MICROSYSTEMS (EUROPE) B.V.; NXP HOLDING 1 B.V.
To: TRIDENT MICROSYSTEMS (FAR EAST) LTD.
Reel/Frame 023928/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2004
From: VAN LAMMEREN, JOHANNES PETRUS MARIA
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 016443/0307 →