Output stage resistant against high voltage swings
View Patent ↗Circuit comprising a signal input ( 11 ) for receiving an input signal (s(t)) and a digital output stage ( 15 ) being designed for operation at a supply voltage (V DD ). The output stage ( 15 ) comprises a series of two n-channel CMOS transistors (no 1 , no 2 ), a common node ( 17 ) between the two n-channel CMOS transistors (no 1 , no 2 ), and an output port ( 16 ). Active voltage limiting means ( 14 ) are arranged between the signal input ( 11 ) and the common node ( 17 ) for limiting voltages (V NM ) at the common node ( 17 ) to a voltage limit (V max ). The voltage limiting means ( 14 ) are controllable byte state of the input signal (s(t)).
1. Circuit comprising
signal input ( 11 ) for receiving an input signal (s(t)),
a digital output stage ( 15 ) being designed for operation at a supply voltage (V DD ), the output stage ( 15 ) comprising
a series of two n-channel CMOS transistors (no 1 , no 2 ; nsw 1 , nsw 2 ) sensitive to voltages across transistor node pairs going beyond a voltage limit (V max ),
a common node ( 17 ; SW 1 ) between the two n-channel CMOS transistors (no 1 , no 2 ; nsw 1 , nsw 2 ),
an output port ( 16 ),
active voltage limiting means ( 14 ; INV 3 , pdio) being arranged between the signal input ( 11 ) and the common node ( 17 ; SW 1 ) for limiting voltages (V max ) at the common node ( 17 ; SW 1 ) to the voltage limit (V max ), the voltage limiting means ( 14 ; INV 2 , pdio) being controllable by the state of the input signal (s(t)) and comprising a plurality of transistors (pd, nd, pswn; INV 3 , pdio) for providing a limited and stable output voltage (V NM ) at the common node ( 17 ; SW 1 ), wherein one of the plurality of transistors is a p-channel CMOS transistor (pswn; pdio) serving as switch, the gate ( 18 ; 38 ) of the p-channel CMOS transistor (pswn; pdio) being controlled by the state of a signal derived from the input signal (s(t)).
2. The circuit of claim 1 , wherein two of the plurality of transistors (pd, nd) are arranged as inverter for inverting the input signal (s(t)) in order to apply an inverted signal (s vn (t)) to a gate ( 18 ; 38 ) of the p-channel CMOS transistor (pswn; pdio) that serves as switch.
3. The circuit of claim 2 , comprising a pull-up resistor (R p ) being situated between the output port ( 16 ) and a node that is kept at a higher voltage (V DDH ) that is greater than the supply voltage (V DD ), the pull-up resistor (R p ) being provided to pull the drain ( 16 ) of one of the two n-channel CMOS transistors (no 2 ) to the higher voltage (V DDH ).
4. The circuit of claim 1 or 2 , comprising a p-channel driver part with at least two p-channel CMOS transistors (po 1 , po 2 ) arranged in series.
5. The circuit of claim 1 or 2 , comprising a level shifter ( 22 ) providing for a voltage (V R ) that is lower than the voltage limit (V max ).
6. The circuit of claim 1 or 2 , comprising speed boost means having at least one capacitive element (C b ) speeding up the turn-on/turn-off behavior of one of the CMOS transistors (no 1 , no 2 ; nsw 1 , nsw 2 ; po 1 , po 2 ).
7. The circuit of claim 6 , wherein the charging of the capacitive element (C b ) depends on the state of a signal derived from the input signal (s(t)).
8. The circuit of claim 1 or 2 being made using a submicron fabrication process, preferably a deep submicron fabrication process.
9. Open-drain output stage comprising a circuit in accordance with one of the claims 1 or 2 .
10. Push-pull-output stage comprising a circuit in accordance with one of the claims 1 or 2 .