Memory array having 2T memory cells
View Patent ↗The present invention relates to a memory array having a plurality of memory cells. In order to combine the compactness of DRAM with the speed and uncomplicated processing profits of SRAM the present invention proposes a memory array having a plurality of memory cells each comprising:—a storage transistor having a drain coupled to a word-line of said array, a source coupled to a bit-line of said array and a gate, and—a control transistor having a drain coupled to the gate of said storage transistor, a source coupled to said bit-line and a gate coupled to said word-line.
1. A memory array having a plurality of memory cells each comprising:
a storage transistor having a drain coupled to a word-line of said array, a source coupled to a bit-line of said array and a gate, and
a control transistor having a drain coupled to the gate of said storage transistor, a source coupled to said bit-line and a gate coupled to said word-line.
2. The memory array of claim 1 , further comprising
means for applying a word-line voltage to said word-line and/or a bit-line voltage to said bit-line and
control means for controlling said word-line voltage so as to define three static states of a memory cell.
3. The memory array of claim 2 ,
wherein said control means are adapted for defining
a pull state by controlling said word-line voltage to be larger than a ground voltage and to be smaller than a difference of a storage voltage provided at the gate of said storage transistor and a threshold voltage of said transistors,
a store state by controlling said word-line voltage to be larger than a difference of said storage voltage and said threshold voltage and to be smaller than a sum of said storage voltage and said threshold voltage, and
a write state by controlling said word-line voltage to be larger than a sum of said storage voltage and said threshold voltage and to be smaller than a supply voltage.
4. The memory array of claim 3 ,
wherein said control means are adapted for controlling said word-line voltage so as to define dynamic operations, in particular a read and a write operation, as transitions between two static states, wherein
a read operation is defined as a transition between said store state and said pull state, and
a write operation is defined as a transition between said store state and said write state.
5. The memory array of claim 4 ,
wherein said control means are adapted to decrease said word-line voltage from a store-level to a read-level to carry out a read operation and to increase said word-line voltage from a store-level to a write-level to carry out a write operation.
6. The memory array of claim 1 ,
wherein low-leakage MOS transistors are used as storage transistor and control transistor.
7. The memory array of claim 1 ,
wherein NMOST or PMOST memory cells are used.
8. The memory array of claim 1 ,
wherein each memory cell comprises further comprises a capacitance coupled between the gate of said storage transistor and ground.
9. A memory cell comprising:
a first transistor, coupled to receive data from a source and to a first command line, that stores the data on a gate of the first transistor;
a second transistor, coupled to the first transistor and a second command line, that controls the read and write function of the first transistor; and
wherein the memory cell does not contain more than two transistors.
10. The memory cell of claim 9 wherein the data is stored within momentary capacitance on the gate of the first transistor.
11. The memory cell of claim 9 wherein the first command line sets a mode for the first transistor.
12. The memory cell of claim 9 wherein the second command line provides enable and disable commands.