Switched-current analogue-to-digital converter
View Patent ↗An current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit ( 120, 130, 135 ) samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit ( 140 ). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits ( 140, 140″ ) may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (S i ′, S i ″) can be multiplexed to double the conversion rate.
1. A current mode pipelined analogue-to-digital converter (ADC) comprising a plurality of serially connected conversion stages (S i ) wherein at least one conversion stage comprises, a stage input for receiving a current (r i-1 ) for conversion, a sample-and-hold (S/H) circuit coupled to sample the current at the stage input during a first time period and to hold the sampled current during a second time period, the S/H circuit having first and second outputs, the first output delivering a mirror of the sampled current during the first time period and a mirror of the held current during the second time period and the second output delivering the held current directly during the second time period, a current comparator means having an input coupled to the first output of the S/H circuit for comparing a current at said input with one or more reference currents, a digital output coupled to an output of the current comparator means for producing a digital signal (D) representing the digital conversion performed by the stage, a digital-to-analogue converter (DAC) having an input coupled to the output of the current comparator means, and a summing means having a first input coupled to an output of the DAC, a second input coupled to the second output of the S/H circuit, and an output for delivering a residual current (r i ) during the second time period.
2. An ADC as claimed in claim 1 , wherein the S/H circuit comprises a plurality of first outputs each delivering a mirror of the sampled current during the first time period and a mirror of the held current during the second time period, and further comprising a plurality of current comparator means each having an input coupled to a respective one of the first outputs of the S/H circuit for comparing a current at said input with one or more respective reference currents, and wherein the digital output is coupled to an output of each of the current comparator means for producing a digital signal (D p , D q ) representing the digital conversion performed by the stage, and wherein the DAC has a plurality of inputs each of said inputs respectively coupled to the output of a respective one of the current comparator means.
3. An ADC as as claimed in claim 1 , wherein the operations during the first and second time periods are interchanged for adjacent conversion stages.
4. An ADC as claimed in claim 3 , comprising two or more pluralities of serially interconnected conversion stages (S′ i , S i ″) operating in parallel wherein the operations during the first and second time periods are multiplexed for corresponding parallel conversion stages.
5. An ADC as as claimed in claim 1 , wherein the current comparator means ( 140 ) comprises a non-regenerative circuit ( 140 ′).
6. An ADC as as claimed in claim 1 , wherein the current comparator ( 140 ) means comprises a regenerative circuit ( 141 ).
7. An electronic device comprising a current mode pipelined analogue-to-digital converter as as claimed in claim 1 .
8. An electronic device as claimed in claim 7 , wherein the electronic device is a wireless receiver or transceiver.