IP Library Granted Patent US 8,537,076
Granted Patent B2
US 8,537,076 · App. 10/524,968 · Granted Sep 17, 2013

Video circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,537,076
App. No.
10/524,968
Granted
Sep 17, 2013
Kind
B2
Abstract

The invention relates to a video circuit ( 1 ) for processing video signals which show images on a display panel with linear light transition, comprising a gamma correction circuit ( 3 ), a quantizer ( 11 ) and a sub-field generator circuit ( 8 ). To save computing time, a random-access memory ( 7 ) replaces the quantizer ( 64 ).

Claims (17)

1. A video circuit for processing video signals which show images on a display panel with linear light transition, comprising

a gamma correction means,

a quantization means, and

a sub-field generation means,

wherein said gamma correction means, said quantization means, and dequantization means are performed in a random-access memory, and the gamma correction means provides gamma-corrected values that have been converted with non-equidistant values,

a filter configured to process the multiple quantization errors of the different neighboring pixels of the current pixel to generate a processing result, wherein the filter comprises multiplier elements, adders and serially connected delay elements;

an adder configured to combine the processing result with the current pixel to generate a combined result; and

further wherein multiple quantization errors of different neighboring pixels of a current pixel are used to generate a pixel value to be displayed on the display panel, wherein the pixel value to be displayed and the multiple quantization errors of the different neighboring pixels satisfy:

PVTBD=rounded ( X (x,y) +CV+α×QE( X (x−1,y−1) )+ b ×QE( X (x,y−1) )+ c× QE( X (x+1,y−1) )+ d× QE( X (x−1,y) ),

where PVTBD represents the pixel value to be displayed, rounded( ) represents a rounding function, CV represents a constant value to perform the rounding function, X(x,y) represents the current pixel that is located in column x and line y of an image, QE(X(x−1,y−1)) represents quantization error of a neighboring pixel that is located in column x−1 and line y−1 of the image, QE(X(x,y−1)) represents quantization error of a neighboring pixel that is located in column x and line y−1 of the image, QE(X(x+1,y−1)) represents quantization error of a neighboring pixel that is located in column x+1 and line y−1 of the image, QE(X(x−1,y)) represents quantization error of a neighboring pixel that is located in column x−1 and line y of the image, and a, b, c and d represent multiplier coefficients for QE(X(x−1,y−1)), QE(X(x,y−1)), QE(X(x+1,y−1)) and QE(X(x−1,y)), respectively, wherein the coefficient a has a value of 1/16, the coefficient b has a value of 5/16, the coefficient c has a value of 3/16 and the coefficient d has a value of 7/16.

2. A video circuit as claimed in claim 1 , wherein an inverse gamma circuit is arranged downstream of the random-access memory.

3. A video circuit as claimed in claim 1 , wherein the random-access memory is said sub-field generating means.

4. A video circuit as claimed in claim 3 , wherein sub-field generation values are applied to a filter via a conversion means and a dequantization means.

5. A video circuit as claimed in claim 4 , wherein the filter applies values to an adder which is situated in an input area of a second signal which represents pixel values of a neighboring line.

6. A video circuit as claimed in claim 5 , wherein sub-field generation values are applied to the adder via a second conversion means and a second dequantization means.

7. A video circuit as claimed in claim 5 , wherein pixel values of the neighboring line are quantized in a quantization means and sub-fields are generated in a further sub-field generation means wherein a further second random-access memory is said further quantization means and said further sub-field generation means.

8. A video circuit as claimed in claim 1 , wherein the constant value is ½.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2021
From: MUFG UNION BANK, N.A.
To: MAXLINEAR, INC.; EXAR CORPORATION; MAXLINEAR COMMUNICATIONS LLC
Reel/Frame 056656/0204 →
SUCCESSION OF AGENCY (REEL 042453 / FRAME 0001) Recorded Jul 1, 2020
From: JPMORGAN CHASE BANK, N.A.
To: MUFG UNION BANK, N.A.
Reel/Frame 053115/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2018
From: MAXLINEAR INC.; ENTROPIC COMMUNICATIONS LLC
To: DYNAMIC DATA TECHNOLOGIES LLC
Reel/Frame 047914/0274 →
SECURITY AGREEMENT Recorded May 12, 2017
From: MAXLINEAR, INC.; ENTROPIC COMMUNICATIONS, LLC (F/K/A ENTROPIC COMMUNICATIONS, INC.); EXAR CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042453/0001 →
MERGER AND CHANGE OF NAME Recorded May 19, 2015
From: ENTROPIC COMMUNICATIONS, INC.; EXCALIBUR SUBSIDIARY, LLC; ENTROPIC COMMUNICATIONS, LLC
To: ENTROPIC COMMUNICATIONS, LLC
Reel/Frame 035717/0628 →
MERGER AND CHANGE OF NAME Recorded May 18, 2015
From: EXCALIBUR ACQUISITION CORPORATION; ENTROPIC COMMUNICATIONS, INC.; ENTROPIC COMMUNICATIONS, INC.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 035706/0267 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: TRIDENT MICROSYSTEMS, INC.; TRIDENT MICROSYSTEMS (FAR EAST) LTD.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 028153/0440 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: NXP
To: NXP HOLDING 1 B.V.
Reel/Frame 023928/0489 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: TRIDENT MICROSYSTEMS (EUROPE) B.V.; NXP HOLDING 1 B.V.
To: TRIDENT MICROSYSTEMS (FAR EAST) LTD.
Reel/Frame 023928/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2005
From: DE GREEF, PETRUS M.; BEUKER, ROB A.
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 017053/0328 →