Integrated circuit with LIN-protocol transmission
The invention relates to an integrated circuit having a system base chip of the kind usually provided for performing transmitting and/or receiving functions at a node that is coupled to a vehicle data bus. In an example embodiment, there is an integrated circuit having a system base chip that has basic functions for a transmitting and/or receiving system for a vehicle data bus, namely at least a system voltage supply, a system reset and a monitoring function An interface circuit that, in a self-contained fashion, runs at least parts of a data bus protocol, and in particular, the LIN (Local Interconnect Network) protocol, that performs detection of the bit-rate of received data, and that is capable of passing on at least one received or transmitted byte. A serial/parallel converter makes use in its conversion of the bit-rate detected by the interface circuit.
1. An integrated circuit comprising:
a base chip including one or more circuits configured to receive a vehicle battery voltage;
convert the vehicle battery voltage to a regulated voltage;
provide the regulated voltage as an output of the integrated circuit;
monitor the vehicle battery voltage;
provide a reset signal in response to the monitoring of the vehicle battery voltage;
receive analog signals from a serial communication interface/universal asynchronous receiver transmitter (SCI/UART) interface, the analog signals corresponding to data formatted for a Local Interconnection Network (LIN) protocol;
identify individual bytes from a digital data signal;
identify a LIN protocol header from at least one of the individual bytes;
detect a bit rate for the received analog signals in response to the detected LIN protocol header and with reference to a clock signal;
convert the analog signals to a digital data signal in response to the detected bit rate;
perform a serial to parallel conversion on the digital data signal; and
provide the parallel-converted digital data signal as an output of the integrated circuit.
2. The integrated circuit of claim 1 , wherein the one or more circuits are further configured to
receive data from a parallel bus input to the integrated circuit;
convert the data from the parallel bus input to a serial form; and
transmit the serial form of the data from the parallel bus input on the SCI/UART interface in response to the detected bit rate.
3. The integrated circuit of claim 1 , wherein the one or more circuits are further configured to provide a watchdog function and in response to the watchdog function provide an interrupt as an output of the integrated circuit.
4. The integrated circuit of claim 1 , wherein the base chip further includes a resistor-capacitor (RC) clock generation circuit that is configured to provide the clock signal.