Adaptive hysteresis for reduced swing signalling circuits
View Patent ↗Apparatus ( 50 ) for processing a differential input signal. The apparatus ( 50 ) comprises a minimum peak detector ( 51 ) with a differential input ( 28 ). The peak detector ( 51 ) provides a first voltage being proportional to an average voltage peak at the peak detector's differential input ( 28 ). A compressor ( 53 ) is provided for processing the first voltage in order to provide a second voltage. The compressor ( 53 ) is followed by a voltage controllable current source providing a trim current that is adjustable by the second voltage. A hysteresis equipped circuit ( 67.1 ) whose hysteresis characteristics are adjustable by the trim current is part of the apparatus ( 50 ).
1. Apparatus for processing a differential clock signal, the apparatus comprising
a peak detector with a differential input, the peak detector configured to provide a first voltage being proportional to an average voltage peak at the peak detector's differential input,
a compressor configured to process the first voltage in order to provide a second voltage,
a voltage controllable current source configured to provide a trim current being adjustable by the second voltage,
a hysteresis equipped circuit having hysteresis characteristics, the hysteresis equipped circuit configured to adjust the hysteresis circuit responsive to the trim current,
wherein the peak detector is operationally coupled to the compressor and the compressor is operationally coupled to the voltage controllable current source.
2. The apparatus of claim 1 , wherein the peak detector comprises an integrator.
3. The apparatus of claim 1 , wherein the peak detector operates on the envelop of a differential input signal being applied to the differential input.
4. The apparatus of claim 1 , wherein the peak detector is designed to constantly follow the average voltage peak at the peak detector's differential input.
5. The apparatus of claim 1 , providing a hysteresis characteristics depending on the average voltage peak at the peak detector's differential input.
6. The apparatus of claim 1 , wherein the peak detector comprises a differential input transistor pair at its differential input.
7. The apparatus of claim 6 , wherein the load conditions of the differential input transistor pair changes when the average voltage peak changes.
8. The apparatus of claim 1 , wherein the hysteresis characteristics are adjusted by shifting trip-levels of the hysteresis equipped circuit to lower levels if the differential input signal is a low level signal and to higher levels if the differential input signal is a high level signal.
9. The apparatus of claim 1 , wherein a differential clock signal is used as the differential input signal to perform a sensing phase and an appropriate adjustment of the hysteresis characteristics.
10. The apparatus of claim 1 , wherein the compressor applies a function when processing the first voltage ( 42 ) in order to provide the second voltage.
11. Control circuitry for a display system comprising an array of interfaces, whereby at least one interface comprises
a peak detector with a differential input, the peak detector configured to provide a first voltage being proportional to an average voltage peak of a differential clock signal being applied to the peak detector's differential input,
a compressor configured to process the first voltage in order to provide a second voltage,
a voltage controllable current source configured to provide a current being adjustable by the second voltage,
a hysteresis equipped circuit having hysteresis characteristics, the hysteresis equipped circuit configured to adjust the hysteresis circuit responsive to the current.
12. The control circuitry of claim 11 , wherein a signal is provided by the at least one interface ( 62 . 1 ) to other interfaces of the array of interfaces in order to allow the hysteresis characteristics of the other interfaces to be adjusted, too.
13. The control circuitry of claim 11 , wherein the interfaces of the array of interfaces serve as differential RSDS interfaces.
14. The control circuitry of claim 11 , wherein the interfaces of the array of interfaces serve as low EMI/low power interfaces between timing controllers and digital-to-analog latches employed for driving analog signals onto column electrodes of a display panel of the display system.
15. The control circuitry of claim 14 , wherein any kind of reduced swing signaling can be used to transmit the video data to the array of interfaces.
16. The control circuitry of claim 11 further comprising a transmitting circuit for transmitting video data to the array of interfaces.
17. The control circuitry of claim 16 , wherein the array of interfaces converts the video data into analog signals for driving onto column electrodes of a display panel of the display system.