Semiconductor light-emitting device and method for manufacturing the same
View Patent ↗A method for fabricating a semiconductor light-emitting element according to the present invention includes the steps of (A) providing a striped masking layer on a first Group III-V compound semiconductor, (B) selectively growing a second Group III-V compound semiconductor over the entire surface of the first Group III-V compound semiconductor except a portion covered with the masking layer, thereby forming a current confining layer that has a striped opening defined by the masking layer, (C) selectively removing the masking layer, and (D) growing a third Group III-V compound semiconductor to cover the surface of the first Group III-V compound semiconductor, which is exposed through the striped opening, and the surface of the current confining layer.
1. A method for fabricating a semiconductor light-emitting element, the method comprising the steps of:
(A) providing a striped masking layer on a first Group III-V compound semiconductor;
(B) selectively growing a second Group III-V compound semiconductor over the entire surface of the first Group III-V compound semiconductor except a portion covered with the masking layer, thereby forming a current confining layer that has a striped opening defined by the masking layer and overhanging portions that overhang the striped opening;
(C) selectively removing the masking layer; and
(D) growing a third Group III-V compound semiconductor to cover the surface of the first Group III-V compound semiconductor, which is exposed through the striped opening, and the surface of the current confining layer, including providing a gap between the first Group III-V compound semiconductor and each of the overhanging portions, the gap not being filled by the third Group III-V compound semiconductor.
2. The method of claim 1 , wherein the step (B) includes growing the second Group III-V compound semiconductor laterally toward the center of the masking layer, thereby defining the overhanging portions for the current confining layer.
3. The method of claim 2 , wherein the step (C) includes removing parts of the masking layer, which are located under the overhanging portions of the current confining layer, thereby making the overhanging portions overhang toward the center of the striped opening.
4. The method of claim 1 , comprising the steps of:
setting the width of the masking layer within the range of 0.5 μm to 3 μm; and
setting the width of a portion of the third Group III-V compound semiconductor, which contacts with the surface of the first Group III-V compound semiconductor through the striped opening, to the range of 0.5 μm to 3 μm.
5. The method of claim 1 , wherein the first Group III-V compound semiconductor has a multilayer structure including an active layer.
6. The method of claim 1 , wherein the Group III-V compound semiconductors are gallium nitride based.
7. The method of claim 6 , wherein the current confining layer includes a gallium nitride layer with aluminum, and has a thickness of 0.1 μm to 0.5 μm.