Single memory with multiple shift register functionality
View Patent ↗The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS 1 -ASz) and at least one access port (P 1 -PZ) for providing access to said memory (EM). Furthermore, access control means (A) are provided for addressing said memory (EM) so as to operate said register memory sections as shift registers and to map shift register accesses of the at least one access port (P 1 to PZ) to predetermined addresses in the global address space of the memory (EM). In this way, it is possible to combine a plurality of FIFO memories in a single addressable memory device. This implementation is favourable in view of power consumption and area. Furthermore, by introducing a buffer memory, a multi-port memory device can be replaced by a single-port memory device of the same capacity. This advanced implementation also provides a reduced cycle and access time.
1. A memory device comprising:
a. a memory having at least two predetermined register memory sections addressable by respective address ranges;
b. at least one access port for providing access to said memory;
c. access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory, said control means being external to said memory and being configured to generate memory addresses for writing to and reading from said memory, and
d. a buffer memory coupled to said at least one access port and to said memory, wherein a line width of said buffer memory and said memory is selected to be greater or equal the data width of said at least one access port multiplied by the sum of read accesses and write accesses per cycle, wherein said address ranges comprise overlapping regions of a predetermined size.
2. A device according to claim 1 , wherein said access control means comprises at least one address counter.
3. A device according to claim 1 , wherein said at least one access port provides access to a plurality of data sources for writing data to respective ones of said register memory sections, and to a plurality of data processing devices for reading data from said register memory sections.
4. A device according to claim 3 , wherein said access control means is arranged to provide alternate access for said data sources and said data processing devices.
5. A device according to claim 3 , wherein data source accesses are controlled to cycle through said global address space, and processing device accesses are controlled to cycle through the address range of a respective register memory section.
6. A device according to claim 1 , wherein said memory is a single-port memory.
7. A device according to claim 1 , wherein said buffer memory is arranged to buffer read and write accesses of said at least one access port.
8. A memory device comprising:
a. a memory having at least two predetermined register memory sections addressable by respective address ranges;
b. at least one access port for providing access to said memory;
c. access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory, said control means being external to said memory and being configured to generate memory addresses for writing to and reading from said memory, and
d. a buffer memory coupled to said at least one access port and to said memory, wherein a line width of said buffer memory and said memory is selected to be greater or equal the data width of said at least one access port multiplied by the sum of read accesses and write accesses per cycle, wherein said at least one access port comprises a plurality of write ports and a plurality of read ports, wherein the number of write ports differs from the number of read ports.
9. A memory device comprising:
a. a memory having at least two predetermined register memory sections addressable by respective address ranges;
b. at least one access port for providing access to said memory;
c. access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory, said control means being external to said memory and being configured to generate memory addresses for writing to and reading from said memory, and
d. a buffer memory coupled to said at least one access port and to said memory, wherein a line width of said buffer memory and said memory is selected to be greater or equal the data width of said at least one access port multiplied by the sum of read accesses and write accesses per cycle, wherein said address control means comprises address translation means for aligning addresses relating to said read accesses in such a way that they fit to said line width.
10. A device according to claim 9 , wherein said address translation means comprises a look-up table.
11. A memory device comprising:
a. a memory having at least two predetermined register memory sections addressable by respective address ranges;
b. at least one access port for providing access to said memory;
c. access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory, said control means being external to said memory and being configured to generate memory addresses for writing to and reading from said memory, and
d. a buffer memory coupled to said at least one access port and to said memory, wherein a line width of said buffer memory and said memory is selected to be greater or equal the data width of said at least one access port multiplied by the sum of read accesses and write accesses per cycle, wherein said access control means is adapted to transfer write accesses to said buffer memory until it is full, and to write one memory line when said buffer memory is full.
12. A memory device comprising:
a. a memory having at least two predetermined register memory sections addressable by respective address ranges;
b. at least one access port for providing access to said memory;
c. access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory, said control means being external to said memory and being configured to generate memory addresses for writing to and reading from said memory, and
d. a buffer memory coupled to said at least one access port and to said memory, wherein a line width of said buffer memory and said memory is selected to be greater or equal the data width of said at least one access port multiplied by the sum of read accesses and write accesses per cycle, wherein said address control means is adapted to align read accesses in such a way that a block of said line width is read all the time.
13. A memory device comprising:
a. a memory having at least two predetermined register memory sections addressable by respective address ranges;
b. at least one access port for providing access to said memory;
c. access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory, said control means being external to said memory and being configured to generate memory addresses for writing to and reading from said memory, and
d. a buffer memory coupled to said at least one access port and to said memory, wherein a line width of said buffer memory and said memory is selected to be greater or equal the data width of said at least one access port multiplied by the sum of read accesses and write accesses per cycle, wherein said at least two predetermined register memory sections are operated as FIFO memory sections.
14. A demultiplexing device for demultiplexing a plurality of input data streams and supplying demultiplexed data streams to a plurality of data processing units, said input data streams being supplied to a memory device, said memory device comprising:
a memory having at least two predetermined register memory sections addressable by respective address ranges;
at least one access port for providing access to said memory; and
access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory,
wherein said demultiplexing device comprises a PRML-based interleaver functionality.
15. A demultiplexing device according to claim 14 , wherein said access control means comprises at least one address counter.
16. A demultiplexing device according to claim 14 , wherein said at least one access port provides access to a plurality of data sources for writing data to respective ones of said register memory sections, and to a plurality of data processing devices for reading data from said register memory sections.
17. A demultiplexing device according to claim 16 , wherein said access control means is arranged to provide alternate access for said data sources and said data processing devices.
18. A multiplexing device for multiplexing data streams supplied from a plurality of data processing units, and for generating multiplexed output data streams, said data streams being supplied to a memory device, said memory device comprising:
a memory having at least two predetermined register memory sections addressable by respective address ranges;
at least one access port for providing access to said memory; and
access control means for addressing said memory so as to operate said register memory sections as shift registers and to map shift register accesses of said at least one access port to predetermined addresses in a global address space of said memory,
wherein said multiplexing device comprises a PRML-based de-interleaver functionality.
19. A multiplexing device according to claim 18 , wherein said at least one access port provides access to a plurality of data sources for writing data to respective ones of said register memory sections, and to a plurality of data processing devices for reading data from said register memory sections.
20. A multiplexing device according to claim 19 , wherein said access control means is arranged to provide alternate access for said data sources and said data processing devices.