IP Library Granted Patent US 8,466,924
Granted Patent B2
US 8,466,924 · App. 10/587,604 · Granted Jun 18, 2013

Displaying on a matrix display

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Quick Facts
Patent No.
US 8,466,924
App. No.
10/587,604
Granted
Jun 18, 2013
Kind
B2
Abstract

A display method comprises the steps of generating ( 1 ) images comprising source data (SDA) and source frame synchronization instants (SSI) having a source frame rate (SFR). The source data (SDA) is stored ( 2 ) in a frame memory ( 5 ) under control of a first address pointer (AP I) having a start address (DSA) being determined by the source frame synchronization instants (SSI). During a read period (RP), display data (DDA) is read ( 2 ) from the memory ( 5 ) under control of a second address pointer (AP 2 ) having a start address (SSA) being determined by display frame synchronization instants (DSI) having a display frame rate (DFR). The display data (DDA) is displayed ( 3 ) on a matrix display ( 4 ). The source frame rate (SIR) or the display frame rate (DFR) is controlled ( 2 ) to obtain, in a stable situation, the first address pointer (AP I) and the second address pointer (AP 2 ) starting with an offset in time (TO) which has a fixed polarity during the read period (RP).

Claims (42)

1. A display method comprising:

generating images comprising source data and source frame synchronization instants having a source frame rate,

storing the source data in a frame memory under control of a first address pointer having a start address being determined by the source frame synchronization instants,

reading during a read period display data from the memory under control of a second address pointer having a start address being determined by display frame synchronization instants having a display frame rate,

displaying the display data on a matrix display, and

controlling the source frame rate or the display frame rate to obtain, in a stable situation, the first address pointer and the second address pointer starting with an offset in time which has a fixed polarity during the read period and a ratio of two between the display frame rate and the source frame rate.

2. A display system comprising:

a video source for generating images comprising source data and source frame synchronization instants having a source frame rate,

means for storing the source data in a frame memory under control of a first address pointer having a start address being determined by the source frame synchronization instants,

means for reading during a read period display data from the memory under control of a second address pointer having a start address being determined by display frame synchronization instants having a display frame rate,

means for displaying the display data on a matrix display and means for controlling the source frame rate or the display frame rate to obtain, in a stable situation, the first address pointer and the second address pointer starting with an offset in time which has a fixed polarity during the read period and a ratio of two between the display frame rate and the source frame rate.

3. A display system as claimed in claim 2 , wherein the means for controlling comprise:

means for comparing the source frame synchronization instants and the display synchronization instants or signals related thereto, and

means for adapting the source frame rate or the display frame rate in response to the comparing to obtain the second pointer always lagging the first pointer during the read period in times or the other way around.

4. A display system claimed in claim 2 , wherein the means for controlling comprise:

means for determining the offset in time between one of the source frame synchronization instants and one of the display frame synchronization instants succeeding each other, and

means for adapting the source frame rate or the display frame rate to obtain a substantially identical source frame rate and display frame rate and a predetermined fixed value of the offset in time.

5. A display system as claimed in claim 4 , wherein the means for adapting are arranged to obtain the offset in time between the first pointer and the second pointer being substantially equal to half a source write period, the source write period being the period in time required for the storing of the source data of one source frame of the source data.

6. A display system as claimed in claim 2 , wherein the means for displaying the display data further comprise:

means for generating a clock signal, and means for generating the display frame synchronization instants using the clock signal, and

wherein the means for controlling the display frame rate comprise means for adapting a frequency of the clock signal.

7. A display system as claimed in claim 2 , wherein the means for displaying the display data further comprise:

means for generating a clock signal, means for generating line instants indicating a start of the lines of the display data using the clock signal, the line instants determining line periods, and

means for generating the display frame synchronization instants using the line instants, and

wherein the means for controlling the display frame rate comprise means for adapting a frequency of the clock signal to vary a duration of the line periods.

8. A display system as claimed in claim 2 , wherein the means for displaying the display data further comprise:

means for generating a clock signal, means for generating line instants indicating a start of the lines of the display data by counting the clock signal, the line instants determining line periods, and

means for generating the display frame synchronization instants using the line instants, and

wherein the means for controlling the display frame rate comprise means for adapting the line periods by varying a number of clock pulses of the clock signal to be counted.

9. A display system method as claimed in claim 2 , wherein a display frame period has a duration being an inverse of the display frame rate and comprises the means for the read period and an idle period,

wherein during the read period, the means for reading are arranged for reading the display data from the memory under control of the second address pointer, and

wherein during the idle period no display data is read from the memory and wherein the means for controlling the display frame rate comprises means for varying the idle time.

10. A display system as claimed in claim 2 , wherein the means for controlling comprise:

means for determining the offset in time, and

means for adapting the display frame rate to obtain a display frame rate being substantially identical to two times the source frame rate and to obtain a predetermined fixed offset in time, by having

(i) the second pointer pointing to a first source video line of an already stored source video frame at an instant preceding the instant the first pointer is pointing to a first source video line a next source video frame to read the first source video line before the first source video line of the next source video frame is stored, and

(ii) the second pointer pointing to a last source video line of the next source video frame at an instant later than an instant the first pointer is pointing to the last source video line of the next source video frame to read the last source video line of the next source video frame after it has been stored.

11. A display system as claimed in claim 2 ,

wherein a display frame period has a duration being an inverse of the display frame rate and comprises the read period and an idle period,

wherein during the read period, the means for reading are arranged for reading the display data from the memory under control of the second address pointer, and wherein during the idle period no display data is read from the memory and

wherein the means for controlling comprise: means for setting a free running display frame rate to a value lower than the value of the source display frame rate wherein a duration of the read period is shorter than a source frame period, and

means for restarting the display frame periods in response to received source synchronization instants.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2021
From: MUFG UNION BANK, N.A.
To: MAXLINEAR, INC.; EXAR CORPORATION; MAXLINEAR COMMUNICATIONS LLC
Reel/Frame 056656/0204 →
SUCCESSION OF AGENCY (REEL 042453 / FRAME 0001) Recorded Jul 1, 2020
From: JPMORGAN CHASE BANK, N.A.
To: MUFG UNION BANK, N.A.
Reel/Frame 053115/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2018
From: MAXLINEAR INC.; ENTROPIC COMMUNICATIONS LLC
To: DYNAMIC DATA TECHNOLOGIES LLC
Reel/Frame 047914/0274 →
SECURITY AGREEMENT Recorded May 12, 2017
From: MAXLINEAR, INC.; ENTROPIC COMMUNICATIONS, LLC (F/K/A ENTROPIC COMMUNICATIONS, INC.); EXAR CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042453/0001 →
MERGER AND CHANGE OF NAME Recorded May 19, 2015
From: ENTROPIC COMMUNICATIONS, INC.; EXCALIBUR SUBSIDIARY, LLC; ENTROPIC COMMUNICATIONS, LLC
To: ENTROPIC COMMUNICATIONS, LLC
Reel/Frame 035717/0628 →
MERGER AND CHANGE OF NAME Recorded May 18, 2015
From: EXCALIBUR ACQUISITION CORPORATION; ENTROPIC COMMUNICATIONS, INC.; ENTROPIC COMMUNICATIONS, INC.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 035706/0267 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: TRIDENT MICROSYSTEMS, INC.; TRIDENT MICROSYSTEMS (FAR EAST) LTD.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 028153/0440 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: NXP
To: NXP HOLDING 1 B.V.
Reel/Frame 023928/0489 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2010
From: TRIDENT MICROSYSTEMS (EUROPE) B.V.; NXP HOLDING 1 B.V.
To: TRIDENT MICROSYSTEMS (FAR EAST) LTD.
Reel/Frame 023928/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2006
From: DE GREEF, PETRUS, M.
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 018157/0040 →