Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase
View Patent ↗A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.
1. A method for reducing leakage current in a read only memory device, comprising the step of:
precharging at least one memory column in said read only memory device during a precharge phase of each read cycle, wherein at least one memory column is not precharged during a standby phase.
2. The method of claim 1 , further comprising the step of terminating said precharge phase by a clock edge.
3. The method of claim 1 , wherein said precharge phase is internally timed out prior to a subsequent clock edge.
4. A read only memory device comprised of memory columns that are connected to a precharge power supply during a precharge portion of each read cycle and are not connected to a precharge power supply during a standby mode.
5. The read only memory device of claim 4 , wherein said read only memory device is further configured to terminate said precharge phase by a clock edge.
6. The read only memory device of claim 4 , wherein said precharge phase is internally timed out prior to a subsequent clock edge.