IP Library Granted Patent US 7,057,254
Granted Patent B2
US 7,057,254 · App. 10/797,324 · Granted Jun 6, 2006

Front illuminated back side contact thin wafer detectors

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Quick Facts
Patent No.
US 7,057,254
App. No.
10/797,324
Granted
Jun 6, 2006
Kind
B2
Abstract

The present invention is directed toward a detector structure, detector arrays, a method of detecting incident radiation, and a method of manufacturing the detectors. The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of cross-talk, and increased flexibility in application. In one embodiment, the present invention comprises a plurality of front side illuminated photodiodes, optionally organized in the form of an array, with both the anode and cathode contact pads on the back side. The front side illuminated, back side contact photodiodes have superior performance characteristics, including less radiation damage, less crosstalk using a suction diode, and reliance on reasonably thin wafers. Another advantage of the photodiodes of the present invention is that high density with high bandwidth applications can be effectuated.

Claims (51)

1. A photodiode array comprising:

a substrate having at least a front side and a back side;

a plurality of photodiodes integrally formed in the substrate forming the said array;

a plurality of electrical contacts in electrical communication with said back side; and

a plurality of suction diodes positioned at selected locations within the array, wherein the fabrication of said array involves a masking process comprising the steps of:

applying a first p+ mask on said front side and

applying a second p+ mask on said back side.

2. The array of claim 1 , wherein said substrate is made of n doped silicon.

3. The array of claim 1 , wherein the substrate is encircled by a metallic ring.

4. The array of claim 3 , wherein silicon underneath the metal ring is doped with an impurity of a selected conductivity type.

5. The array of claim 1 , wherein each of said plurality of photodiodes and suction diodes have a front surface, back surface, and side walls and wherein said side walls are covered by a first insulating layer, a first conducting layer, and a second insulating layer.

6. The array of claim 5 wherein the first insulating layer is an oxide.

7. The array of claim 5 wherein the second insulating layer is an oxide.

8. The array of claim 5 wherein the conductive layer is doped poly-silicon.

9. The array of claim 5 wherein the second insulating layer is in physical communication with a filler.

10. The array of claim 9 wherein the filler is undoped poly-silicon.

11. The array of claim 1 wherein each of said photodiodes has a middle layer juxtaposed between a front layer and a back layer.

12. The array of claim 11 wherein said middle layer comprises a doped material of n conductivity type.

13. The array of claim 11 wherein said back layer comprises an n+ layer in electrical communication with a metal to form a cathode.

14. The array of claim 11 wherein said front layer comprises a doped material of p+ conductivity type.

15. The array of claim 14 wherein front p+ layer is in electrical communication with a metal to form an anode.

16. A photodiode comprising:

a substrate having a front side and a back side;

a front layer;

a back layer; and

a detecting region juxtaposed between said front layer and said back layer; wherein said photodiode is adjacent to a connection region having a first insulating layer, a first conducting layer, and a second insulating layer and wherein said photodiode is made using a process comprising the steps of:

applying a first p+ mask on said front side;

applying a second p+ mask on said back side; and

forming said connection region using a hole cutting technique.

17. The photodiode of claim 16 wherein said process for making the photodiode further comprises the step of diffusing boron.

18. The photodiode of claim 16 wherein said process for making the photodiode further comprises the step of performing a p+ doping of the connection region.

19. The photodiode of claim 16 wherein said each of said connection region has a diameter of at or about 125 micron.

20. The photodiode of claim 16 wherein at least one of said connection regions functions as a conduit for forming an electrical connection between said first layer and a back surface electrical contact.

21. The photodiode of claim 16 wherein said front layer comprises a doped material of p+ conductivity type and said front p+ layer is in electrical communication with a metal to form an anode.

22. A photodiode array comprising:

a substrate having at least a front side and a back side;

a plurality of photodiodes integrally formed in the substrate forming the said array wherein each of said photodiodes has a middle layer juxtaposed between a front layer and a back layer;

a plurality of electrical contacts in electrical communication with said back side; and

a plurality of suction diodes positioned at selected locations within the array, wherein the fabrication of said array involves a masking process comprising the steps of:

applying a first n+ mask on said front side and

applying a second n+ mask on said back side.

23. The array of claim 22 wherein said middle layer comprises a doped material of p conductivity type.

24. The array of claim 22 wherein said back layer comprises a p+ layer in electrical communication with a metal to form a anode.

25. The array of claim 22 wherein said front layer comprises a doped material of n+ conductivity type.

26. The array of claim 25 wherein front n+ layer is in electrical communication with a metal to form a cathode.

27. The array of claim 22 , wherein the substrate is encircled by a metallic ring.

28. The array of claim 27 , wherein silicon underneath the metal ring is doped with an impurity of a selected conductivity type.

29. The array of claim 22 , wherein each of said plurality of photodiodes and suction diodes have side walls wherein said side walls are covered by a first insulating layer, a first conducting layer, and a second insulating layer.

30. The array of claim 29 wherein the first insulating layer is an oxide.

31. The array of claim 29 wherein the second insulating layer is an oxide.

32. The array of claim 29 wherein the conductive layer is doped polysilicon.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jul 1, 2025
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: OSI OPTOELECTRONICS, INC.
Reel/Frame 071581/0725 →
TERMINATION OF SECURITY INTEREST IN PATENTS Recorded Oct 21, 2010
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, SUCCESSOR-BY-MERGER TO WACHOVIA BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: OSI OPTOELECTRONICS, INC.
Reel/Frame 025169/0282 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Oct 19, 2010
From: OSI OPTOELECTRONICS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 025150/0964 →
CHANGE OF NAME Recorded Nov 16, 2007
From: UDT SENSORS, INC.
To: OSI OPTOELECTRONICS, INC.
Reel/Frame 020119/0639 →
NOTICE OF GRANT OF SECURITY INTEREST Recorded Aug 13, 2007
From: OSI OPTOELECTRONICS, INC.
To: WACHOVIA BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 019679/0364 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2005
From: BUI, PETER STEVEN; TANEJA, NARAYAN DASS
To: UDT SENSORS, INC.
Reel/Frame 016673/0266 →