Low profile wire bond for an electron sensing device in an image intensifier tube
View Patent ↗An electron sensing device for receiving electrons from an output surface of an electron gain device has a silicon die including an active surface area for positioning below the output surface of an electron gain device. The silicon die also includes a silicon step formed below and surrounding the active surface area, and a first array of bond pads formed on the silicon step for providing output signals from the silicon die. When the electron sensing device is positioned below the electron gain device, a tight vertical clearance is formed between the output surface of the electron gain device and the active surface area of the electron sensing device.
1. An electron sensing device for receiving electrons from an output surface of an electron gain device, the electron sensing device comprising:
a silicon die including an active surface area for positioning below the output surface of an electron gain device,
wherein the silicon die includes a silicon step formed below and surrounding the active surface area, and
a first array of bond pads formed on the silicon step for providing output signals from the silicon die,
wherein when the electron sensing device is positioned below the electron gain device, a tight vertical clearance is formed between the output surface of the electron gain device and the active surface area of the electron sensing device, and
an array of terminals disposed on a periphery of the active surface area of the silicon die, and
an array of conductive stripes extending between the array of terminals and the first array of bond pads,
wherein each conductive stripe includes an end terminating at the first array of bond pads positioned below another end terminating at the array of terminals.
2. The electron sensing device of claim 1 including
a ceramic carrier for holding the silicon die, and
a second array of bond pads disposed on the ceramic carrier for making electrical contacts to the first array of bond pads.
3. The electron sensing device of claim 1 wherein
the tight vertical clearance includes a vertical spacing of less than 100 microns, and
a vertical spacing between the output surface of the electron gain device and the first array of bond pads is greater than the tight vertical clearance.
4. The electron sensing device of claim 1 having active sensors including one of complementary metal oxide semiconductor (CMOS) sensors, charge coupled device (CCD) sensors, electron bombarded CMOS (EBCMOS) sensors, EBCCD sensors, and avalanche photo detector (APD) sensors.
5. An electron sensing device for receiving electrons from an output surface of an electron gain device, the electron sensing device comprising:
a silicon die including an active surface area for positioning below the output surface of the electron gain device,
an array of terminals disposed on a periphery of the active surface area of the silicon die,
an array of conductive stripes extending horizontally from the array of terminals to a diced end wall of the silicon die and bending downwardly to extend along the diced end wall of the silicon die,
a ceramic carrier positioned below the silicon die, including a plurality of pins for providing input/output signals to/from the silicon die, and
electrical connections formed between the array of conductive stripes and the plurality of pins,
wherein when the electron sensing device is positioned below the electron gain device, a tight vertical clearance is formed between the output surface of the electron gain device and the active surface area of the electron sensing device.
6. The electron sensing device of claim 5 wherein
the electrical connections include solder balls for forming electrical contacts between the array of conductive stripes and the plurality of pins.
7. The electron sensing device of claim 5 wherein
the tight vertical clearance includes a vertical spacing of less than 100 microns.
8. The electron sensing device of claim 5 having active sensors including one of CMOS sensors, CCD sensors, electron bombarded CMOS (EBCMOS) sensors, EBCCD sensors and avalanche photo detector (APD) sensors.
9. An electron sensing device for receiving electrons from an output surface of an electron gain device, the electron sensing device comprising:
a silicon die including an active surface area for positioning below the output surface of the electron gain device,
an array of first bond pads disposed on a periphery of the active surface area of the silicon die,
a ceramic carrier positioned below the silicon die, including a second array of bond pads disposed on the ceramic carrier and arranged to surround the first array of bond pads, and
a flexible decal having first and second frame borders, including conductive stripes extending between the first and second frame borders,
wherein when the flexible decal is pressed onto the silicon die and the ceramic carrier, the conductive stripes form electrical connections between the first array of bond pads and the second array of bond pads.
10. The electron sensing device of claim 9 wherein when the electron sensing device is positioned below the electron gain device, a tight vertical clearance is formed between the output surface of the electron gain device and the active surface area of the electron sensing device.
11. The electron sensing device of claim 10 wherein the tight vertical clearance includes a vertical spacing of less than 100 microns.
12. The electron sensing device of claim 9 wherein the ceramic carrier includes a plurality of pins electrically connected to the second array of bond pads for providing an input/output signal interface.
13. A first integrated circuit (IC) having a first surface area disposed in close proximity to a second surface area of a second IC, the first and second surface areas providing signal transfer between the first IC and the second IC, the first IC comprising:
a silicon die including the first surface area for positioning below the second surface area of the second IC,
wherein the silicon die includes a silicon step formed below and surrounding the first surface area, and
a first array of bond pads formed on the silicon step for providing signal transfer from the silicon die,
wherein when the first IC is positioned below the second IC, a tight vertical clearance is formed between the first surface area and the second surface area, and
an array of terminals disposed on a periphery of the active surface area of the silicon die, and
an array of conductive stripes extending between the array of terminals and the first array of bond pads,
wherein each conductive stripe includes an end terminating at the first array of bond pads positioned below another end terminating at the array of terminals.
14. The first IC of claim 13 including
a ceramic carrier for holding the silicon die, and
a second array of bond pads disposed on the ceramic carrier for making electrical contacts to the first array of bond pads.
15. The first IC of claim 13 wherein
the tight vertical clearance includes a vertical spacing of less than 100 microns, and
a vertical spacing between the first surface area of the first IC and the first array of bond pads is greater than the tight vertical clearance.
16. A first integrated circuit (IC) having a first surface area disposed in close proximity to a second surface area of a second IC, the first and second surface areas providing signal transfer between the first IC and the second IC, the first IC comprising:
a silicon die including the first surface area for positioning below the second surface area of the second IC,
an array of first bond pads disposed on a periphery of the first surface area of the silicon die,
a ceramic carrier positioned below the silicon die, including a second array of bond pads disposed on the ceramic carrier and arranged to surround the first array of bond pads, and
a flexible decal having first and second frame borders, including conductive stripes extending between the first and second frame borders,
wherein when the flexible decal is pressed onto the silicon die and the ceramic carrier, the conductive stripes form electrical connections between the first array of bond pads and the second array of bond pads.
17. The first IC of claim 16 wherein when the first IC is positioned below the second IC, a tight vertical clearance is formed between the first surface area of the first IC and the second surface area of the second IC.
18. The electron sensing device of claim 17 wherein the tight vertical clearance includes a vertical spacing of less than 100 microns.
19. The electron sensing device of claim 16 wherein the ceramic carrier includes a plurality of pins electrically connected to the second array of bond pads for providing an input/output signal interface.