Semiconductor device
View Patent ↗The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.
1. A semiconductor integrated circuit device comprising:
an interface circuit including a first MOSFET having a first threshold voltage;
a main circuit including a second MOSFET having a second threshold voltage lower than the first threshold voltage;
a substrate bias voltage generator to generate a substrate bias voltage for the second MOSFET;
a step-down voltage power supply circuit;
a substrate bias monitor circuit to monitor a value of the substrate bias voltage; and
a third MOSFET to control a power supply to the main circuit,
wherein the interface circuit is arranged to interface with the external of the semiconductor integrated circuit device and with the main circuit,
wherein the interface circuit is arranged to be supplied with a first supply voltage and the main circuit is arranged to be supplied with a second supply voltage lower than the first supply voltage,
wherein the substrate bias voltage generator is arranged to be supplied with the first supply voltage;
wherein the step-down voltage power supply circuit produces the second supply voltage from the first supply voltage, and
wherein the first supply voltage is supplied from an external device of the semiconductor integrated circuit device; and:
wherein the third MOSFET is controlled to turn on when the substrate bias monitor circuit detects that the substrate bias voltage is ensured to be sufficiently stable.
2. The semiconductor integrated circuit device according to claim 1 , wherein a threshold voltage of the third MOSFET is higher than the second threshold voltage.
3. A semiconductor integrated circuit device comprising:
an interface circuit including a first MOSFET having a first threshold voltage;
a main circuit including a second MOSFET having a second threshold voltage lower than the first threshold voltage;
a substrate bias voltage generator to generate a substrate bias voltage for the second MOSFET, and
a step-down voltage power supply circuit;
wherein the interface circuit is arranged to interface with the external of the semiconductor integrated circuit device and with the main circuit,
wherein the interface circuit is arranged to be supplied with a first supply voltage and the main circuit is arranged to be supplied with a second supply voltage lower than the first supply voltage,
wherein the substrate bias voltage generator is arranged to be supplied with the first supply voltage;
wherein the step-down voltage power supply circuit produces the second supply voltage from the first supply voltage,
wherein the first supply voltage is supplied from an external device of the semiconductor integrated circuit device,
wherein the interface circuit comprises:
a third MOSFET and a fourth MOSFET;
wherein the third and fourth MOSFETs are arranged in parallel; and
wherein the gates of the third and fourth MOSFETs are arranged to receive a first signal from the external of the semiconductor integrated circuit device.
4. A semiconductor integrated circuit device comprising:
an interface circuit including a first MOSFET having a first threshold voltage;
a main circuit including a second MOSFET having a second threshold voltage lower than the first threshold voltage;
a substrate bias voltage generator to generate a substrate bias voltage for the second MOSFET;
a step-down voltage power supply circuit; and
a third MOSFET and a fourth MOSFET;
wherein the interface circuit is arranged to interface with the external of the semiconductor integrated circuit device and with the main circuit,
wherein the interface circuit is arranged to be supplied with a first supply voltage and the main circuit is arranged to be supplied with a second supply voltage lower than the first supply voltage,
wherein the substrate bias voltage generator is arranged to be supplied with the first supply voltage;
wherein the step-down voltage power supply circuit produces the second supply voltage from the first supply voltage,
wherein the first supply voltage is supplied from an external device of the semiconductor integrated circuit device,
wherein the third and fourth MOSFETs are arranged in parallel; and
wherein the drains of the third and fourth MOSFETs are arranged to output a second signal to the external of the semiconductor integrated circuit device.