Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same

1. A manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:

(a) forming a first insulator over a main surface of a semiconductor substrate, and forming a first gate electrode on said first insulator so that a taper angle of a lowermost portion of a sidewall of said first gate electrode with respect to the main surface of said semiconductor substrate can be within a range of 95 to 180 degrees except for 180 degrees;

(b) forming a second insulator over the sidewall of said first gate electrode, and forming a third insulator on the surface of said semiconductor substrate on both sides of said first gate electrode;

(c) forming a fourth insulator on said second insulator and said third insulator;

(d) forming a fifth insulator on said fourth insulator; and

(e) forming a second gate electrode made of a conductive material on the sidewall of said first gate electrode and at a position opposite to said semiconductor surface on one or both sides of said first gate electrode via said second to fifth insulators.

2. The manufacturing method of a nonvolatile semiconductor memory device according to claim 1 ,

wherein said taper angle is within a range of 95 to 150 degrees except for 150 degrees.

3. The manufacturing method of a nonvolatile semiconductor memory device according to claim 2 ,

wherein said second insulator is formed by dry oxidation or ISSG oxidation.

4. The manufacturing method of a nonvolatile semiconductor memory device according to claim 1 ,

wherein said taper angle is within a range of 100 to 180 degrees except for 180 degrees.

5. The manufacturing method of a nonvolatile semiconductor memory device according to claim 4 ,

wherein said taper angle is within a range of 100 to 150 degrees except for 150 degrees.

6. The manufacturing method of a nonvolatile semiconductor memory device according to claim 5 ,

wherein said second insulator is formed by wet oxidation.

7. The manufacturing method of a nonvolatile semiconductor memory device according to claim 1 ,

wherein a taper angle formed by said fourth insulator is within a range of 95 to 180 degrees except for 180 degrees.

8. A manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:

(a) forming a first insulator over a main surface of a semiconductor substrate, forming a first semiconductor layer on said first insulator, and forming a cap insulator on said first semiconductor layer;

(b) patterning said cap insulator;

(c) forming a first gate electrode by recessing said first semiconductor layer to an edge portion of said cap insulator with using said cap insulator as a mask;

(d) forming a second insulator on a sidewall of said first gate electrode, and forming a third insulator on the surface of said semiconductor substrate on both sides of said first gate electrode;

(e) forming a fourth insulator on said second and third insulators;

(f) forming a fifth insulator on said fourth insulator;

(g) forming a second gate electrode made of a conductive material in a self-aligned manner on the sidewall of said first gate electrode and at a position opposite to said semiconductor surface on one or both sides of said first gate electrode via said second to fifth insulators; and

(h) forming a sixth insulator in a self-aligned manner on a side surface of said second gate electrode and siliciding the surface of said first gate electrode, the surface of said second gate electrode, and a part of the surface of said semiconductor substrate,

wherein an recess amount of said first semiconductor layer in said step (c) is one-third or more of a gate length of said second gate electrode.

9. The manufacturing method of a nonvolatile semiconductor memory device according to claim 8 ,

wherein the recess amount of said second gate electrode is from one-third or more of the gate length of said second gate electrode to the gate length thereof.

10. A manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:

(a) forming a first insulator over a main surface of a semiconductor substrate, and forming a first gate electrode on said first insulator;

(b) when a spacer is formed at a position being in contact with a sidewall of said first gate electrode and a surface of said semiconductor substrate disposed on one or both sides of said first gate electrode, forming a lowermost portion of a surface being out of contact with said first gate electrode into a round shape;

(c) forming a second insulator on said spacer and forming a third insulator on the surface of said semiconductor substrate on both sides of said first gate electrode;

(d) forming a fourth insulator on said second and third insulators;

(e) forming a fifth insulator on said fourth insulator; and

(f) forming a second gate electrode made of a conductive material on a sidewall of said first gate electrode and at a position opposite to said semiconductor surface on both sides of said gate electrode via said spacer and said second to fifth insulators.

11. The manufacturing method of a nonvolatile semiconductor memory device according to claim 1 ,

wherein said second gate electrode is formed so that a step between an upper edge of said first gate electrode and an upper edge of said second gate electrode has a height of 20 nm or more in a direction vertical to the main surface of said semiconductor substrate.

12. The manufacturing method of a nonvolatile semiconductor memory device according to claim 1 ,

wherein said fifth insulator is formed by ISSG oxidation.

13. The manufacturing method of a nonvolatile semiconductor memory device according to claim 1 ,

wherein said fourth insulator is formed by CVD.

14. The manufacturing method of a nonvolatile semiconductor memory device according to claim 1 ,

wherein said fourth insulator is a silicon nitride film.