IP Library Granted Patent US 7,533,312
Granted Patent B2
US 7,533,312 · App. 10/902,237 · Granted May 12, 2009

System and method for testing of electronic circuits

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,533,312
App. No.
10/902,237
Granted
May 12, 2009
Kind
B2
Abstract

The system and method of the present invention combine multiple tests ( 15 ) into a batch and submit the batch for processing to exercise electronic circuits, for example, a managed network ( 25 ) such as a wireless network. The system and method insure that tests ( 15 ) are timely run by utilization of a batch submit trigger ( 42 ). When a test ( 15 ) has completed, the system and method return the results ( 11 ) of that particular test ( 15 ) to the user, regardless of whether or not the rest of the tests ( 15 ) in the batch have completed execution.

Claims (41)

1. A system for testing at least one electronic circuit comprising:

a test preparer capable of combining a plurality of pre-selected tests into a batch;

a test queue capable of i) formatting the batch to cause test execution code to view the ore-selected tests of the batch as a single test with multiple test cases, and ii) submitting said batch to a test queue maintained by the test execution code, the test execution code executing said plurality of pre-selected tests in said batch, the test execution code providing results from executing said plurality of pre-selected tests; and

a test results manager capable of monitoring said results, said test results manager capable of retrieving said results for each of said plurality of pre-selected tests regardless if all of said plurality of pre-selected tests have completed execution,

wherein said plurality of pre-selected tests is capable of testing the at least one electronic circuit.

2. The system as defined in claim 1 wherein said plurality of pre-selected tests comprises:

a wireless test.

3. The system as defined in claim 1 wherein said test preparer comprises:

a batch submit trigger capable of determining when said batch is complete.

4. The system as defined in claim 3 wherein said batch submit trigger comprises a timer and a capacity limit.

5. The system as defined in claim 3 wherein said batch submit trigger is user-selectable.

6. The system as defined in claim 1 wherein said test results manager comprises:

a test deleter capable of deleting said batch and said results after said results have been retrieved for all of said plurality of pre-selected tests.

7. The system as defined in claim 1 wherein said test preparer is capable of combining a polymorphic set of tests in said batch.

8. A method for testing of at least one electronic circuit comprising the steps of:

(a) combining a plurality of tests into a batch, said plurality of tests capable of testing the at least one electronic circuit;

(b) formatting the batch to cause a test execution environment to view the tests of the batch as a single test with multiple test cases;

(c) submitting the batch to a test execution environment test queue;

(d) executing the plurality of tests in the batch; and

(e) providing the results of the executed plurality of tests to a data sink, said step of providing the results happening substantially synchronously with the completion of each of said plurality of tests,

wherein said step of combining takes place substantially within pre-defined time constraints of the plurality of tests.

9. The method as defined in claim 8 further comprising the step of:

deleting the batch and the results after the results are returned from all of the plurality of tests.

10. The method as defined as in claim 8 further comprising the step of:

substantially adhering to the pre-defined time constraints by conforming to a batch submit trigger.

11. The method as defined in claim 10 wherein the batch submit trigger comprises a batch timer and a batch size threshold.

12. The method as defined in claim 8 further comprising the step of executing steps (a)-(e) within a computer node.

13. The method as defined in claim 8 further comprising the step of executing steps (a)-(e) within a communications network including at least one computer node.

14. The method as defined in claim 8 further comprising the step of enabling a computer data signal embodied in electromagnetic signals traveling over a communications network to carry information capable of causing a computer node in the communications network to execute steps (a)-(e).

15. The method as defined in claim 8 further comprising the step of providing a computer readable medium having instructions embodied therein for executing steps (a)-(e).

16. A system for testing at least one electronic circuit:

means for combining a plurality of tests into a batch;

means for formatting the batch to cause a test execution environment to view the tests of the batch as a single test with multiple test cases;

means for submitting said batch to a test execution environment test queue;

means for executing the plurality of tests in said batch; and

means for providing the results of the executed plurality of tests to at least one data sink, said means for providing said results happening substantially synchronously with completing each of said plurality of tests,

wherein said means for combining takes place substantially within pre-defined time constraints of the plurality of tests, and wherein the plurality of tests is capable of testing the at least one electronic circuit.

17. The system as defined in claim 16 further comprising:

means for deleting the batch and the results after the results are provided from all of said plurality of tests.

18. The system as defined as in claim 16 further comprising:

means for substantially adhering to said pre-defined time constraints by conforming to a batch submit trigger.

Assignments (5)
TERMINATIONS OF SECURITY INTEREST AT REEL 052729, FRAME 0321 Recorded Jan 5, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: VIAVI SOLUTIONS INC.; RPC PHOTONICS, INC.
Reel/Frame 058666/0639 →
SECURITY INTEREST Recorded May 21, 2020
From: VIAVI SOLUTIONS INC.; 3Z TELECOM, INC.; ACTERNA LLC; ACTERNA WG INTERNATIONAL HOLDINGS LLC; VIAVI SOLUTIONS LLC; JDSU ACTERNA HOLDINGS LLC; OPTICAL COATING LABORATORY, LLC; RPC PHOTONICS, INC.; TTC INTERNATIONAL HOLDINGS, LLC
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 052729/0321 →
CHANGE OF NAME Recorded Nov 6, 2015
From: JDS UNIPHASE CORPORATION
To: VIAVI SOLUTIONS INC.
Reel/Frame 037057/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2013
From: AGILENT TECHNOLOGIES, INC.
To: JDS UNIPHASE CORPORATION
Reel/Frame 030088/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2004
From: JANES, MR. STEPHEN D.
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 015266/0825 →