Method and apparatus for variable delay data transfer
View Patent ↗A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was received, whereas a slow bypass mode provides received cache data within the subsequent master clock cycle. A queue mode provides a programmable amount of delay to be used by the cache interface device, whereby consecutive queue mode provides a First In First Out (FIFO) operation to consecutively retrieve queued data. A block queue mode, on the other hand, provides a method to retrieve queued data using a programmable offset so as to enable partial cache line retrieval without the need to use No Operation (NoP) clock cycles on the cache interface data bus.
1. A method of data transfer using programmable delay, comprising:
providing a plurality of alternative data paths, each of the data paths being programmably selectable based on a state of one or more control signals, and each of the data paths providing a different data transfer delay to reach an output register;
receiving a data block at a first instant in time within a first master clock cycle;
determining one of a plurality of master clock cycles to be used as a second master clock cycle;
programmably selecting one of the alternative data paths based on the state of the one or more control signals to utilize its corresponding data transfer delay in providing the data block to the output register to accommodate a data storage mechanism between an external cache and a front side bus, wherein at least one of the data transfer delays comprises an amount of time greater than the first master clock cycle; and
transmitting the received data block from the output register at a second instant in time within the second master clock cycle.
2. The method according to claim 1 , wherein the second master clock cycle is selected to be the same as the first master clock cycle.
3. The method according to claim 2 , wherein the data transfer delay minimizes the difference between the first and second instants in time.
4. The method according to claim 1 , wherein the second master clock cycle is selected to be different than the first master clock cycle.
5. The method according to claim 4 , wherein the second master clock cycle is selected to be immediately subsequent in time to the first master clock cycle.
6. The method according to claim 4 , wherein an amount of time equal to at least one master clock cycle separates the second master clock cycle from the first master clock cycle.
7. The method according to claim 6 , wherein data queuing is used to provide the amount of separation time equal to the at least one master clock cycle.
8. The method according to claim 7 , wherein write addressing is used to store a plurality of received data blocks, wherein the plurality of received data blocks represent components of at least one cache line.
9. The method according to claim 8 , wherein read addressing is used to retrieve the plurality of received data blocks.
10. The method according to claim 9 , wherein consecutive read addressing is used to retrieve whole cache lines.
11. The method according to claim 9 , wherein offset read addressing is used to consecutively retrieve data blocks representative of partial cache lines.
12. An apparatus coupled to a data storage mechanism between an external cache and a front side bus, the apparatus comprising:
an output register;
an input register configured to receive a data block;
a plurality of alternative data paths each suitable for transferring the data block from the input register to the output register in accordance with a master clock signal;
a controller having inputs to receive control signals, wherein different states of the control signals respectively correspond to different delay modes to accommodate the data storage mechanism, and having outputs to activate one of the plurality of alternative data paths to programmably effect a desired one of the delay modes based on the state of the control signals; and
wherein the activated one of the data paths comprises means for delaying the transfer of the data block to the output register for a duration different than a transfer delay of the other data paths, and wherein at least one of the delay modes delays transfer of the data block by an amount of time greater than a single cycle of the master clock signal.
13. The apparatus as in claim 12 , wherein one of the plurality of alternative data paths comprises a fast bypass data path comprising a multiplexer coupled to the controller to enable the multiplexer to directly transfer the data block from the input register to the output register in response to the control signals indicating a fast bypass delay mode.
14. The apparatus as in claim 12 , wherein one of the plurality of alternative data paths comprises a slow bypass data path comprising:
one or more intermediate registers coupled between the input register and the output register; and
one or more multiplexers coupled to the controller to enable the one or more intermediate registers to delay the transfer of the data block from the input register to the output register relative to the master clock signal in response to the control signals indicating a slow bypass delay mode.
15. The apparatus as in claim 12 , wherein one of the plurality of alternative data paths comprises a queue data path comprising:
a register array coupled to the input register to store the data block and configured to output the stored data block in response to a triggering control signal;
one or more intermediate registers coupled between the register array and the output register; and
means for enabling the transfer of the data to be delayed from the register array to the output register relative to the master clock signal in response to the control signals indicating a queue delay mode.
16. A method comprising:
providing a plurality of alternative data paths for transferring a data block from an input to an output of a device in accordance with a master clock signal;
providing a plurality of programmable delay modes, and wherein at least one of the programmable delay modes delays transfer of the data block by an amount of time greater than a single cycle of the master clock signal to accommodate a data storage mechanism between an external cache and a front side bus;
receiving the data block at the input of the device;
selecting one of the different data paths in which to direct the data block as a function of which of the configurable delay modes is active; and
delaying delivery of the data block to the output of the device for a time that is dependent upon the selected data path that has been selected as a function of the active configurable delay modes.