Semiconductor memory
View Patent ↗A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R 3 and R 4 , which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R 3 and R 4 . Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R 1 - 1 , R 1 - 2 and R 2 , and the absolute value is adjusted based on a resistance ratio of resistors R 3 and R 4.
1. A semiconductor memory comprising:
a circuit for reading a data from a memory cell to one of a complementary bit line pair, and giving a reference potential for determining a value of the data to the other thereof; and
a potential generator circuit for giving temperature dependency to the reference potential based on a potential having temperature dependency,
the potential generator circuit independently controlling an absolute value and the temperature dependency of the reference potential.
2. The memory according to claim 1 , wherein the reference potential increases proportional to a rise of temperature.
3. The memory according to claim 1 , wherein when a temperature range is A[K]<T<B[K] (A and B are arbitrary numbers, T is temperature, K is absolute temperature), the reference potential is variable on a straight line connecting an intermediate value of the minimum value of “1” read potential distribution and the maximum value of “0” read potential distribution in temperature A[K], and an intermediate value of the minimum value of the “1” read potential distribution and the maximum value of the “0” read potential distribution in temperature B[K].
4. The memory according to claim 1 , wherein the reference potential increases with a rise of temperature in a range lower than temperature C[K] (C is an arbitrary number and K is absolute temperature) while decreasing with a rise of temperature in a range higher than the temperature C[K].
5. The memory according to claim 1 , wherein when a temperature range is A[K]<T<B[K] (A and B are arbitrary numbers, T is temperature, K is absolute temperature), the reference potential is variable on the following first and second straight lines:
the first straight line connecting an intermediate value of the minimum value of “1” read potential distribution and the maximum value of “0” read potential distribution in temperature A[K], and an intermediate value of the minimum value of the “1” read potential distribution and the maximum value of the “0” read potential distribution in temperature C[K](A<B<C);
the second straight line connecting an intermediate value of the minimum value of “1” read potential distribution and the maximum value of “0” read potential distribution in temperature C[K], and an intermediate value of the minimum value of the “1” read potential distribution and the maximum value of the “0” read potential distribution in temperature B[K].
6. The memory according to claim 3 , wherein the straight line is expressed by the following equation
VDC=y ×(α+β× T )
where, y, α and β are each constant, and VDC is equivalent to an output potential.
7. The memory according to claim 1 , wherein the potential generator circuit includes:
a BGR circuit for outputting a potential having temperature dependency; and
first and second resistors series-connected between an output terminal of the BGR circuit and a ground point,
an output potential is output from a connection point of the first and second resistors.
8. The memory according to claim 7 , wherein the BGR circuit includes:
a first current path composed of first diode, third and fourth resistors, which are series-connected between the output terminal and the ground point;
a second current path composed of a second diode and a fifth resistor, which are series-connected between the output terminal and the ground point;
an operational amplifier having a first input terminal connected to a connection point of the third and fourth resistors, and a second input terminal connected to a connection point of the second diode and the fifth resistor; and
a MOS transistor having a gate connected to an output terminal of the operational amplifier, a source connected to a power supply terminal, and a drain connected to the output terminal thereof.
9. The memory according to claim 1 , wherein the potential generator circuit includes:
a BGR circuit having a first output terminal for outputting a potential having temperature dependency, and a second output terminal for outputting a potential having no temperature dependency; and
first and second resistors series-connected between the first output terminal and a ground point,
an output potential is output from a connection point of the first and second resistors.
10. The memory according to claim 9 , wherein the BGR circuit includes:
a first current path composed of first diode, third and fourth resistors, which are series-connected between the first output terminal and the ground point;
a second current path composed of a second diode and a fifth resistor, which are series-connected between the second output terminal and the ground point;
a third current path composed of a third diode, sixth and seventh resistors, which are series-connected between the second output terminal and the ground point;
a first operational amplifier having a first input terminal connected to a connection point of the third and fourth resistors, a second input terminal connected to a connection point of the second diode and the fifth resistor, and an output terminal connected to the first output terminal; and
a second operational amplifier having a first input terminal connected to a connection point of the sixth and seventh resistors, a second input terminal connected to a connection point of the second diode and the fifth resistor, and an output terminal connected to the second output terminal.
11. The memory according to claim 1 , wherein the potential generator circuit includes: a diode having temperature dependency; and first and second resistors series-connected between the diode and a ground point, and carries a current to a current path composed of the diode, the first and second resistors based on a potential having no temperature dependency,
an output potential is output from a connection point of the first and second resistors.
12. The memory according to claim 1 , wherein the potential generator circuit includes:
a BGR circuit for outputting a potential having no temperature dependency; and
a converter for outputting an output potential having temperature dependency based on the potential output from the BGR circuit,
the converter includes:
a first current path composed of first and second resistors and a MOS transistor, which are series-connected between a power supply terminal and a ground point;
an operational amplifier having a first input terminal connected to a connection point of the first and second resistors, a second input terminal supplied with the potential output from the BGR circuit, and an output terminal connected to a gate of the MOS transistor; and
a second current path composed of a diode, third and fourth resistors, which are series-connected between a drain of the MOS transistor and the ground point,
an output potential is output from a connection point of the third and fourth resistors.
13. The memory according to claim 1 , wherein the potential generator circuit includes:
a monitor circuit for outputting a potential having no temperature dependency; and
a converter for outputting an output potential having temperature dependency based on the potential output from the monitor circuit,
the converter comprising:
a diode and a MOS transistor, which are series-connected between a power supply terminal and a first node;
first and second resistors connected between the first node and a ground point; and
an operational amplifier having a first input terminal connected to the first node, a second input terminal supplied with a potential having no temperature dependency, output from the monitor circuit, and an output terminal connected to a gate of the MOS transistor,
an output potential being output from a connection point of the first and second resistors.
14. The memory according to claim 1 , wherein the potential generator circuit includes:
a monitor circuit for outputting a potential having no temperature dependency; and
a converter for outputting an output potential having temperature dependency based on the potential output from the monitor circuit,
the converter comprising:
a first current path composed of a first diode and a MOS transistor, which are series-connected between a power supply terminal and a first node;
a second current path composed of a second diode and a MOS transistor, which are series-connected between the first node and a ground point;
an operational amplifier having a first input terminal connected to a drain of the MOS transistor, a second input terminal supplied with the potential output from the monitor circuit, and an output terminal connected to a gate of the MOS transistor,
an output potential being output from a connection point of the first and second resistors.
15. The memory according to claim 1 , wherein the potential generator circuit includes:
a diode having an anode supplied with a sense amplifier drive potential, and a cathode connected to one terminal of a first resistor; and
a second resistor connected between the other terminal of the first resistor and a ground point,
an output potential being output from a connection point of the first and second resistors.
16. The memory according to claim 1 , wherein the potential generator circuit includes:
a first diode having an anode supplied with a sense amplifier drive potential, and a cathode connected to a first node;
a second diode having an anode connected to a second node, and a cathode connected to a ground point;
first and second resistors connected between the first and second nodes;
a current path composed of a MOS transistor, third and fourth resistors and, which are series-connected between a power supply terminal and a ground point;
an operational amplifier having a first input terminal connected to a drain of the MOS transistor, a second input terminal connected to a connection point of the first and second resistors, and an output terminal connected to a gate of the MOS transistor,
an output potential being output from a connection point of the first and second resistors.
17. The memory according to claim 1 , wherein the potential generator circuit includes:
a BGR circuit for outputting a potential having no temperature dependency; and
a converter for outputting an output potential having temperature dependency based on the potential output from the BGR circuit,
the converter includes:
a first current path composed of first and second resistors, first and second MOS transistors, which are series-connected between a power supply terminal and a ground point;
an operational amplifier having a first input terminal connected to a connection point of the first and second resistors, a second input terminal supplied with the potential output from the BGR circuit, and an output terminal connected to a gate of the first MOS transistor; and
a second current path composed of third and fourth resistors, and a third MOS transistor, which are series-connected between the power supply terminal and the ground point;
a fourth MOS transistor having a gate connected to a drain of the first MOS transistor, and a source connected to the power supply terminal, a sense amplifier drive potential being output from the drain,
the second MOS transistor being connected to the diode,
a gate of the third MOS transistor being connected to the drain of the first MOS transistor,
an output potential being output from a connection point of the third and fourth resistors.
18. The memory according to claim 17 , wherein the sense amplifier drive potential has a value having temperature dependency, and the drains of the first and third MOS transistors have a potential equal to each other.
19. A semiconductor memory comprising:
a bit line having a reference potential;
a dummy capacitor composed of a MOS transistor;
a first potential generator circuit for charging a gate of the MOS transistor, for generating the reference potential, wherein a gate of the MOS transistor is connected to the bit line; and
a second potential generator circuit for driving source and drain of the MOS transistor and a substrate,
one of a first output potential output from the first potential generator circuit and a second output potential output from the second potential generator circuit having temperature dependency, while the other having no temperature dependency.
20. The memory according to claim 19 , wherein the first potential generator circuit includes:
a BGR circuit for outputting a potential having temperature dependency; and
first and second resistors series-connected between an output terminal of the BGR circuit and a ground point,
the first output potential being output from a connection point of the first and second resistors,
the BGR circuit including:
a first current path composed of a first diode, third and fourth resistors, which are series-connected between the output terminal and the ground point;
a second current path composed of a second diode and a fifth resistor, which are series-connected between the output terminal and the ground point;
an operational amplifier having a first input terminal connected to a connection point of the third and fourth resistors, a second input terminal connected to a connection point of the second diode and the fifth resistor; and
a MOS transistor having a gate connected to an output terminal of the operational amplifier, a source connected to a power supply terminal, and a drain connected to the output terminal thereof.