Semiconductor integrated circuit
A semiconductor integrated circuit capable of accurately measuring a time lag difference in operation test wiring is disclosed. It is provided with nMOS transistors in which each control terminal is connected to a signal terminal of a memory macro. Since the nMOS transistors are turned off when the test signals TCLK, TWE, and TRE are all at a low level, the potential of a pad which is connected to a drain is pulled up by a current generator. When the signal TCLK is changed to a high level, the transistor is turned on and the potential of the pad is changed to a low level. Then, a time lag from the moment at which the signal TCLK is changed to a high level to the moment at which the pad is changed to a low level is measured. Similarly, a time lag from the moment at which the signal TWE is changed to a high level to the moment at which the pad is changed to a low level and a time lag from the moment at which the signal TRE is changed to a high level to the moment at which the pad is changed to a low level are respectively measured. A difference of the measurement times corresponds to a difference of the time lags taken for the signals TCLK, TWE, and TRE to arrive at the memory macro.
1 . A semiconductor integrated circuit having a circuit to be checked through an operation test, a plurality of pads for receiving test signals from outside, and a plurality of signal paths formed within another circuit in order to lead the test signals entered from the pads to a signal input terminal of the checked circuit in an operation test mode, comprising
a first test pad to which a first pull-up potential is supplied, and
a time lag measuring circuit including a plurality of first transistors in each of which one end is connected to the first test pad, the other end is connected to a power source line, and a control terminal is connected to the corresponding signal input terminal.
2 . The semiconductor integrated circuit according to claim 1 , comprising
a second test pad to which a second pull-up potential is supplied, and
the time lag measuring circuit including
a second transistor in which one end is connected to the second test pad, the other end is connected to the power source line, and a control terminal is connected to a signal output terminal of the checked circuit,
a third transistor in which one end is connected to the second test pad, the other end is connected to the power source line, and a control terminal is connected to a third test pad, and
a fourth transistor in which one end is connected to the first test pad, the other end is connected to the power source line, and a control terminal is connected to the third test pad.
3 . The semiconductor integrated circuit according to claim 2 , in which
the first test pad is a pad for use in receiving or supplying another signal in a usual operation mode,
a switch transistor is provided between the first test pad and the one end of the first transistor as well as a power source of the first pull-up potential, and
the switch transistor is turned off in the usual operation mode and turned on in the operation test mode.
4 . The semiconductor integrated circuit according to claim 1 , in which
the first test pad is a pad for use in receiving or supplying another signal in a usual operation mode,
a switch transistor is provided between the first test pad and the one end of the first transistor as well as a power source of the first pull-up potential, and
the switch transistor is turned off in the usual operation mode and turned on in the operation test mode.
5 . A semiconductor integrated circuit having a circuit to be checked through an operation test and another circuit for creating an operation control signal of the checked circuit according to a signal entered from outside, comprising
an input switch for supplying the operation control signal to the checked circuit at a time of measuring a current consumption of the whole semiconductor integrated circuit and making output high impedance at a time of measuring a current consumption of the circuit excepting the checked circuit,
an output switch for supplying an output signal of the checked circuit to the other circuit at a time of measuring a current consumption of the whole semiconductor integrated circuit and making output high impedance at a time of measuring a current consumption of the circuit excepting the checked circuit, and
a pseudo signal supplying circuit for supplying a pseudo output signal of the checked circuit to the other circuit at a time of measuring a current consumption of the circuit excepting the checked circuit.
6 . The semiconductor integrated circuit according to claim 5 , in which
the pseudo signal supplying circuit is wiring for supplying the pseudo output signal entered from a test pad to the other circuit.
7 . The semiconductor integrated circuit according to claim 5 , in which
the pseudo signal supplying circuit is a pseudo signal switch for making output high impedance at a time of measuring a current consumption of the whole semiconductor integrated circuit and supplying the pseudo output signal entered from a predetermined pad to the other circuit at a time of measuring a current consumption of the circuit excepting the checked circuit.
8 . The semiconductor integrated circuit according to claim 5 , in which
the pseudo signal supplying circuit is a pseudo signal generator for making output high impedance at a time of measuring a current consumption of the whole semiconductor integrated circuit and supplying one or all of the operation control signal to the other circuit at a time of measuring a current consumption of the circuit excepting the checked circuit.