Microcomputer and microprocessor having flash memory operable from single external power supply
View Patent ↗A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.
1. A semiconductor integrated circuit device on a semiconductor substrate, comprising:
a processing unit;
an electrically erasable and programmable non-volatile memory including a memory array and a peripheral circuit which controls a read operation, an erase operation and a programming operation of the memory array, wherein the memory array includes a plurality of electrically erasable and programmable non-volatile memory cells, each of which has a layer to store electrons, wherein the memory array has a first area to be stored therein with data for a program to be executed by the processing unit and a second area to be stored therein with information; and
a volatile memory circuit capable of storing the information therein,
wherein, in response to an initialization operation of the semiconductor integrated circuit device, the information in the second area is read out from the second area and is stored in the volatile memory circuit so that the peripheral circuit is controlled by the information in the volatile memory circuit.
2. A semiconductor integrated circuit device according to claim 1 ,
wherein the initialization operation includes a reset operation.
3. A semiconductor integrated circuit device according to claim 1 ,
wherein the layer includes a floating gate, and
wherein the plurality of electrically erasable and programmable non-volatile memory cells each includes the floating gate and a control gate.
4. A semiconductor integrated circuit device according to claim 1 ,
wherein the information includes trimming data.
5. A semiconductor integrated circuit device according to claim 4 ,
wherein the peripheral circuit includes an internal voltage generating circuit which provides internal voltages including an erase voltage and a programming voltage, and
wherein voltage levels of the internal voltages provided from the internal voltage generating circuit are controlled by the trimming data.