IP Library Granted Patent US 7,324,788
Granted Patent B2
US 7,324,788 · App. 11/036,180 · Granted Jan 29, 2008

RF integrated circuit comprising a frequency synthesizer not very sensitive to injection locking

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Quick Facts
Patent No.
US 7,324,788
App. No.
11/036,180
Granted
Jan 29, 2008
Kind
B2
Abstract

The present invention relates to an RF integrated circuit comprising a frequency synthesizer and a QAM modulator for modulating a baseband signal of frequency F BB , the frequency synthesizer supplying to the QAM modulator an output signal of frequency F 1 adjustable with a frequency step ΔF 1 , for forming a carrier signal of the QAM modulator. According to the present invention, the frequency synthesizer is a Vernier effect frequency synthesizer comprising an auxiliary frequency synthesizer supplying an auxiliary signal of frequency F 2 adjustable with a frequency step ΔF 2 and a main frequency synthesizer having a phase-locked loop bandwidth at least two times higher than the frequency step ΔF 2 of the auxiliary signal.

Claims (43)

1. An RF integrated circuit of a frequency synthesizer and a QAM modulator for modulating a baseband signal of frequency F BB , the frequency synthesizer supplying to the QAM modulator an output signal of frequency F 1 adjustable with a frequency step ΔF 1 , for forming a carrier signal of the QAM modulator,

characterised in that the frequency synthesizer is a Vernier effect frequency synthesizer comprising:

an auxiliary frequency synthesizer supplying an auxiliary signal of frequency F 2 adjustable with a frequency step ΔF 2 , and

a main frequency synthesizer supplying the output signal of frequency F 1 and having a phase-locked loop for mixing the output signal of frequency F 1 with the auxiliary signal of frequency F 2 , such that the frequency step ΔF 1 of the output signal is equal or proportional to the frequency step ΔF 2 of the auxiliary signal,

and in that the bandwidth of the phase-locked loop of the main frequency synthesizer is as least two times higher than the frequency step ΔF 2 of the auxiliary signal.

2. The RF integrated circuit according to claim 1 wherein the deviation between the frequencies F 2 and F 1 is higher than ten times the baseband frequency F BB .

3. The RF integrated circuit according to claim 1 wherein the main frequency synthesizer comprises a voltage-controlled oscillator supplying the output signal of frequency F 1 , and a phase comparator receiving at input a comparison signal of determined frequency and a subtractive component of frequency F 2 −F 1 supplied by the means for mixing the output signal of frequency F 1 with the auxiliary signal of frequency F 2 .

4. The RF integrated circuit according to claim 3 wherein the frequency of the comparison signal is at least 20 times higher than the frequency step ΔF 2 of the auxiliary signal.

5. The RF integrated circuit according to claim 3 wherein the comparison signal is a fixed frequency signal, such that the frequency step ΔF 1 of the output signal is equal to the frequency step ΔF 2 of the auxiliary signal.

6. The RF integrated circuit according to claim 3 wherein the main frequency synthesizer comprises a frequency divider of rank P receiving the auxiliary signal at input and supplying the comparison signal, such that the output signal has a frequency step ΔF 1 equal to the frequency step ΔF 2 of the auxiliary signal multiplied by a term that varies according to P.

7. The RF integrated circuit according to claim 3 wherein the frequency F 2 −F 1 of the subtractive component is in the order of 300 MHz.

8. The RF integrated circuit according to claim 1 wherein the auxiliary frequency synthesizer comprises a voltage-controlled oscillator and a phase-locked loop, the voltage-controlled oscillator of the auxiliary frequency synthesizer supplying the auxiliary signal, the phase-locked loop of the auxiliary frequency synthesizer enabling the frequency F 2 of the auxiliary signal to be adjusted.

9. The RF integrated circuit according to claim 8 wherein the auxiliary frequency synthesizer is driven by a quartz oscillator linked to a frequency divider of rank R that supplies a comparison signal of determined frequency to the phase-locked loop of the auxiliary frequency synthesizer.

10. The RF integrated circuit according to claim 1 wherein the frequency F 2 of the auxiliary signal is higher than the frequency F 1 of the output signal.

11. The RF integrated circuit according to claim 1 wherein the frequency F 1 of the output signal is on the order of 3 to 4 GHz.

12. The RF integrated circuit according to claim 1 wherein the phase-locked loop of the main frequency synthesizer has a bandwidth between 1 and 30 MHz.

13. The RF integrated circuit according to claim 1 wherein the frequency step ΔF 1 of the output signal is on the order of 400 KHz.

14. A method for reducing the injection locking effect in an RF integrated circuit having:

a frequency synthesizer and a QAM modulator for modulating a baseband signal of frequency F BB , the frequency synthesizer supplying to the QAM modulator an output signal of frequency F 1 adjustable with a frequency step ΔF 1 , for forming a carrier signal of the QAM modulator, the method comprising:

using, as a frequency synthesizer, a Vernier effect frequency synthesizer;

supplying an auxiliary signal of frequency F 2 adjustable with a frequency step ΔF 2 , and

supplying the output signal of frequency F 1 ;

mixing the output signal of frequency F 1 with the auxiliary signal of frequency F 2 , such that the frequency step ΔF 1 of the output signal is equal or proportional to the frequency step ΔF 2 of the auxiliary signal; and

selecting the bandwidth of the first phase-locked loop to be at least two times higher than the frequency step ΔF 2 of the auxiliary signal.

15. The method according to claim 14 , wherein the deviation between the frequencies F 2 and F 1 is chosen to be higher than 50 times the baseband frequency F BB .

16. The method according to claim 14 wherein the main frequency synthesizer comprises a voltage-controlled oscillator supplying the output signal of frequency F 1 , and a phase comparator receiving at input a comparison signal of determined frequency and a subtractive component of frequency F 2 -F 1 supplied by the means for mixing the output signal of frequency F 1 with the auxiliary signal of frequency F 2 .

17. The method according to claim 16 wherein the frequency of the comparison signal is chosen to be at least 20 times higher than the frequency step ΔF 2 of the auxiliary signal.

18. The method according to claim 16 wherein the comparison signal is obtained by dividing the frequency F 2 of the auxiliary signal by a number P, such that the output signal has a frequency step ΔF 1 equal to the frequency step ΔF 2 of the auxiliary signal multiplied by a term that varies according to P.

19. The method according to claim 16 wherein the frequency F 2 -F 1 of the subtractive component is in the order of 300 MHz.

20. The method according to claim 14 wherein the frequency F 2 of the auxiliary signal is chosen to be higher than the frequency F 1 of the output signal.

21. The method according to claim 14 wherein the frequency F 1 of the output signal is in the order of 3 to 4 GHz.

22. The method according to claim 14 wherein the phase-locked loop of the main frequency synthesizer has a bandwidth between 1 and 30 MHz.

23. The method according to claim 14 wherein the frequency step ΔF 1 of the output signal is in the order of 400 KHz.

24. A frequency synthesizer for providing an output to a QAM modulator for modulating a baseband signal of frequency, the frequency synthesizer being a Vernier effect frequency synthesizer comprising:

a first output stage that outputs a signal of frequency F 1 adjustable with a frequency step ΔF;

an auxiliary frequency synthesizer supplying an auxiliary signal of frequency F 2 adjustable with a frequency step ΔF 2 ;

a main frequency synthesizer supplying the output signal of frequency F 1 to the output stage;

a mixer that receives the output signal of a frequency F 1 and mixes the signals F 1 and F 2 ;

a phase-locked loop circuit that receives the output of the mixer of the output signal of frequency F 1 with the auxiliary signal of frequency F 2 and adjusts the frequency step ΔF 1 of the output signal to be equal or proportional to the frequency step ΔF 2 of the auxiliary signal, the bandwidth of the phase-locked loop of the main frequency synthesizer being at least two times higher than the frequency step ΔF 2 of the auxiliary signal.

25. The frequency synthesizer according to claim 24 further including:

a filter positioned between the output of the mixer and the phase-locked loop such that the signal passes through a filter before entering the phase locked loop.

26. The frequency synthesizer according to claim 24 further including:

a frequency divider positioned between the output of the mixer and the input of the phase-locked loop.

Assignments (5)
CHANGE OF NAME Recorded Feb 2, 2016
From: ST WIRELESS SA
To: ST-ERICSSON SA
Reel/Frame 037683/0128 →
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2016
From: STMICROELECTRONICS S.A. (FKA SGS-THOMSON MICROELECTRONICS S.A.)
To: ST WIRELESS SA
Reel/Frame 037650/0697 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2007
From: JOUEN, PHILIPPE
To: STMICROELECTRONICS, S.A.
Reel/Frame 020201/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2005
From: RAMET, SERGE; TRIAIRE, PASCAL
To: STMICROELECTRONICS S.A.
Reel/Frame 015975/0689 →