Nonvolatile semiconductor memory having a charge accumulation layer connected to a gate
View Patent ↗At least either above or below a memory transistor formed on an insulating substrate, a shielding layer which has an area larger than that of the semiconductor layer of the memory transistor and has either an electromagnetic wave shielding effect or a light shielding effect or both of these is provided, and by this shielding layer, electromagnetic waves or light is prevented from entering the semiconductor layer. Or, the regional area of at least one of the gate and the charge accumulation layer of the memory transistor is made larger than the semiconductor layer to prevent electromagnetic waves or light from entering the semiconductor layer by the gate or the charge accumulation layer.
1. A nonvolatile semiconductor memory comprising:
an insulating substrate;
a memory transistor formed on said insulating substrate, said memory transistor including
a semiconductor layer having a source region, a drain region, and a channel region formed between said source region and said drain region,
a charge accumulation layer separated from said channel region by a first insulating layer, and
a first gate separated from said charge accumulation layer by a second insulating layer; and
a shielding layer having an electromagnetic wave shielding effect or a light shielding effect, or having both the electromagnetic shielding effect and the light shielding effect formed on at least one of the upper side or the lower side of said memory transistor, wherein said shielding layer is a semiconductor material doped with metal impurities.
2. The nonvolatile semiconductor memory according to claim 1 , wherein said shielding layer is formed in an area larger than said semiconductor layer so as to cover the portion immediately below or immediately above the semiconductor layer.
3. The nonvolatile semiconductor memory according to claim 1 , wherein in said memory transistor, said charge accumulation layer is formed on said channel region via said first insulating layer, and said first gate is formed on said charge accumulation layer via said second insulating layer.
4. The nonvolatile semiconductor memory according to claim 3 , wherein said memory transistor further has a second gate that is formed below said channel region and separated from said channel region by a third insulating layer.
5. The nonvolatile semiconductor memory according to claim 1 , wherein said insulating substrate is formed of glass or plastic.
6. The nonvolatile semiconductor memory according to claim 1 , wherein said shielding layer is formed on both the upper side and the lower side of said memory transistor.
7. A nonvolatile semiconductor memory comprising:
an insulating substrate;
a memory transistor formed on said insulating substrate, said memory transistor including
a semiconductor layer having a source region, a drain region, and a channel region formed between said source region and said drain region,
a charge accumulation layer separated from said channel region by a first insulating layer, and
a first gate separated from said charge accumulation layer by a second insulating layer; and
a shielding layer having an electromagnetic wave shielding effect or a light shielding effect, or having both the electromagnetic shielding effect and the light shielding effect formed on at least one of the upper side or the lower side of said memory transistor,
wherein in said memory transistor, said charge accumulation layer is formed on said first gate via said second insulating layer, and said channel region is formed on said charge accumulation layer via said first insulating layer, and
wherein said shielding layer is a semiconductor material doped with metal impurities.
8. The nonvolatile semiconductor memory according to claim 7 , wherein said memory transistor further has a second gate that is formed above said channel region and separated from said channel region by a third insulating layer.
9. A nonvolatile semiconductor memory comprising:
an insulating substrate;
a memory transistor formed on said insulating substrate, said memory transistor including
a semiconductor layer having a source region, a drain region, and a channel region formed between said source region and said drain region,
a charge accumulation layer separated from said channel region by a first insulating layer, and
a first gate separated from said charge accumulation layer by a second insulating layer; and
a shielding layer having an electromagnetic wave shielding effect or a light shielding effect, or having both the electromagnetic shielding effect and the light shielding effect formed on at least one of the upper side or the lower side of said memory transistor,
wherein said shielding layer is one of tungsten silicide, amorphous silicon or chromium.