IP Library Granted Patent US 7,161,212
Granted Patent B2
US 7,161,212 · App. 11/052,224 · Granted Jan 9, 2007

Thin film transistor, liquid crystal display using thin film transistor, and method of manufacturing thin film transistor

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Quick Facts
Patent No.
US 7,161,212
App. No.
11/052,224
Granted
Jan 9, 2007
Kind
B2
Abstract

A semiconductor film, which is located over a gate electrode for forming a channel region between a source electrode and a drain electrode, has a width greater than a width of the source electrode and a width of the drain electrode located over the gate electrode. Irregularities are formed in a width direction of the semiconductor film on both edge portions in the channel region.

Claims (9)

1. A thin film transistor comprising:

a semiconductor film extending between a source electrode and a drain electrode, said semiconductor film including irregularities formed on both edges thereof along extending direction of the semiconductor film and in a direction orthogonal to the extending direction, a concave portion of the irregularities being located outside a region sandwiched by a pair of virtual straight lines linking both ends of opposed edges of said source electrode and said drain electrode; and

a gate electrode disposed below said channel region with interposing a gate insulating film between said semiconductor film and said gate electrode.

2. A liquid crystal display comprising:

an active matrix substrate on which thin film transistors are formed; and

a counter substrate opposed to said active matrix substrate for interposing a liquid crystal layer,

wherein each of said thin film transistors includes:

a semiconductor film extending between a source electrode and a drain electrode, said semiconductor film including irregularities formed on both edges thereof along extending direction of the semiconductor film and in a direction orthogonal to the extending direction, a concave portion of the irregularities being located outside a region sandwiched by a pair of virtual straight lines linking both ends of opposed edges of said source electrode and said drain electrode; and

a gate electrode being disposed below said channel region with interposing a gate insulating film between said semiconductor film and said gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2023
From: GOLD CHARM LIMITED
To: HANNSTAR DISPLAY CORPORATION
Reel/Frame 063351/0517 →