IP Library Granted Patent US 7,224,606
Granted Patent B2
US 7,224,606 · App. 11/067,976 · Granted May 29, 2007

Semiconductor memory device and method of controlling semiconductor memory device

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Quick Facts
Patent No.
US 7,224,606
App. No.
11/067,976
Granted
May 29, 2007
Kind
B2
Abstract

A semiconductor memory device has a nonvolatile memory cell to which data writing operation is limited to a predetermined logic value. In the case of rewriting data “10101010” written in a first memory core to data “01010101”, since the data writing operation includes writing of a logic value “1” opposite to the predetermined logic value, an erasing operation is needed and the data writing is regulated. By rewriting a pointer value stored in a pointer memory in place of performing the erasing operation, an operation of switching a memory core to be selected to a second memory core (data “11111111”) is performed. Data is newly written into the second memory core selected by the rewritten pointer value.

Claims (11)

1. A semiconductor memory device comprising:

plural memory cores having nonvolatile memory cells in which data to be written is regulated to a predetermined logic value and each of which is to be independently subjected to access control; and

a pointer having nonvolatile memory cells, the number of the pointer nonvolatile memory cells equal to the number of said memory cores−1, and the pointer selecting the memory core to be subjected to the access control.

2. The semiconductor memory device according to claim 1 , wherein memory core nonvolatile memory cells and pointer nonvolatile memory cells are flash memory cells on which only programming operation can be performed.

3. The semiconductor memory device according to claim 1 , wherein the pointer selects the same memory core both in the data writing operation and a data reading operation.

4. The semiconductor memory device according to claim 3 , wherein when the data writing operation is performed on the nonvolatile memory cells in the memory core selected,

in the case where all of data to be written by the data writing operation has the predetermined logic value, the data writing operation is performed on the nonvolatile memory cells in the memory core, and

in the case where at least one bit of data to be written by the data writing operation has a logic value opposite to the predetermined logic value, the nonvolatile memory cells in the pointer is rewritten and the data writing operation is performed on another memory core selected by the pointer after the rewriting.

5. The semiconductor memory device according to claim 1 , wherein the pointer is a read pointer, and

the read pointer selects at least any one of the plural memory cores in which plural candidate values are preliminarily written at the time of selecting a setting value for setting an internal state from the plural candidate values in a predetermined range.

6. The semiconductor memory device according to claim 5 , wherein the same value is written in at least one of the candidate values in plural memory cores.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →