Pulsed arbitration system and method
View Patent ↗A pulsed arbitration system has a partial-address coincidence detector with a partial-address collision flag as an output. An active global word line detector and disable pulse generator receives the partial-address collision flag as well as a decoded row address and an internal write pulse as an input, and generates a disable pulse for the interfering global word line of the colliding reading port.
1. A pulsed arbitration systems comprising:
a partial-address coincidence detector having a partial-address collision flag as an output; and
an active global word line detector and disable pulse generator receiving the partial-address collision flag as well as a decoded row address and an internal write pulse as an input.
2. The system of claim 1 , wherein the partial-address coincidence detector has a plurality of partial port addresses as input signals.
3. The system of claim 2 , wherein the plurality of partial port addresses does not include any global word line addresses.
4. The system of claim 1 , wherein the partial-address coincidence detector includes a read/write detector.
5. The system of claim 1 , wherein an output pulse of the active global word line detector and disable pulse generator has a pulse width related to a writing port's internal write pulse width.
6. The system of claim 5 , wherein a trailing edge of the output pulse deactivates the partial-address collision flag output.
7. The system of claim 1 , wherein the partial-address coincidence detector detects a partial-address collision between two or more ports.
8. A method of pulsed arbitration, comprising:
(a) determining if a partial-address coincidence exists between a plurality of ports;
b) when the partial-address coincidence exists between the plurality of ports, generating a partial-address collision flag and potentially a disable pulse.
9. The method of claim 8 , wherein (b) further includes:
(b1) determining if one of the plurality of ports is attempting a write operation;
(b2) when one of the plurality of ports is attempting the write operation and the partial; address coincidence exists, generating the disable pulse.
10. The method of claim 8 , wherein (a) further includes:
(a1) determining if two or more of the plurality of ports are attempting a write;
(a2) when two or more of the plurality of ports are attempting the write, blocking all attempted operations.
11. The method of claim 8 , further including:
(c) determining an interfering global word line.
12. The method of claim 11 , further including:
(d) applying the disable pulse to the interfering global word line.
13. The method of claim 8 , wherein (b) further includes:
(b1) determining a pulse Width of the disable pulse.
14. The method of claim 13 , further including:
(b2) determining a delay period of the disable pulse.
15. A pulsed arbitration system, comprising:
a partial-address coincidence detector having a partial-address collision flag as an output; and
a disable circuit coupled to the partial-address coincidence detector.
16. The system of claim 15 , wherein the partial-address coincidence detector has a write detector.
17. The system of claim 16 , wherein the partial-address coincidence detector is not coupled to any global word lines.
18. The system of claim 17 , wherein the disable circuit includes an active global word line detector.
19. The system of claim 18 , wherein the disable circuit includes a disable pulse delay circuit.
20. The system of claim 19 , wherein the disable circuit includes a disable pulse width generator.