Dither amplitude correction for constant current drivers
View Patent ↗In satisfying the above need, as well as overcoming the enumerated drawbacks and other limitations of the related art, the present invention provides an improved switched driver circuit. As disclosed above, there is a need to compensate for the high impedance load characteristics in certain implementations of hysteretic switching constant current drivers. The switching waveform of switching constant current driver circuits may be modified in such a way that retains the important dither characteristics and improves system level performance.
1. A switched driver circuit for generating a switched drive signal including a dither waveform, the switched driver circuit comprising:
a dither generator circuit having a clock input and being configured to generate a dither signal based on the clock input;
a gate control circuit configured to generate the switched drive signal based on the dither signal;
a dither correction circuit being configured to suspend the dither signal based on a signal parameter of the switched drive signal.
2. The switched driver circuit according to claim 1 , wherein the signal parameter is a magnitude of the switched drive signal.
3. The switched driver circuit according to claim 1 , wherein the signal parameter is a frequency of the switched drive signal.
4. The switched driver circuit according to claim 1 , further comprising:
a first comparator in electrical communication with the dither generator circuit and configured to generate an upper threshold signal based on the dither signal;
a second comparator in electrical communication with the dither generator circuit and configured to generate a lower threshold signal based on the dither signal;
wherein the dither correction circuit is configured to suspend the dither signal based on the upper or lower threshold signal.
5. The switched driver circuit according to claim 4 , wherein the dither correction circuit is configured to suspend the dither signal when the upper or lower threshold signal is not received within a predefined time period.
6. The switched driver circuit according to claim 5 , wherein the predefined time period is ½ of the dither period.
7. The switched driver circuit according to claim 4 , wherein the first and second comparator are configured to receive a feedback signal based on the switched drive signal.
8. The switched driver circuit according to claim 4 , wherein the dither correction circuit is configured to disable the clock input of the dither generator when the upper or lower threshold signal is not received within a predefined time period.
9. The switched driver circuit according to claim 8 , wherein the predefined time period is ½ of the dither period.
10. The switched driver circuit according to claim 4 , wherein the dither correction circuit is configured to selectively suspend the dither signal based on either the upper or lower threshold signal.
11. The switched driver circuit according to claim 1 , wherein the dither correction circuit is configured to enable the dither signal when a predefined time period expires.
12. A switched driver circuit for generating a switched drive signal including a dither waveform, the switched driver circuit comprising:
a dither generator circuit having a clock input and being configured to generate a dither signal based on the clock input;
a first comparator in electrical communication with the dither generator circuit and configured to generate an upper threshold signal based on the dither signal;
a second comparator in electrical communication with the dither generator circuit and configured to generate a lower threshold signal based on the dither signal;
a gate control circuit in electrical communication with the first and second comparator to receive the upper and lower threshold signal, the gate control circuit being configured to generate the switched drive signal;
a dither correction circuit in electrical communication with the first and second comparator to receive the upper and lower threshold signal, the dither correction circuit being configured to suspend the dither signal when the upper or lower threshold signal is not received within a first predefined time period.
13. The switched driver circuit according to claim 12 , wherein the first predefined time period is ½ of the dither period.
14. The switched driver circuit according to claim 12 , wherein the dither correction circuit is configured to disable the clock input of the dither generator when the upper or lower threshold signal is not received within the first predefined time period.
15. The switched driver circuit according to claim 12 , wherein the dither correction circuit is configured to selectively suspend the dither signal based on either the upper or lower threshold signal.
16. The switched driver circuit according to claim 12 , wherein the dither correction circuit is configured to enable the dither signal when a second predefined time period expires.
17. The switched driver circuit according to claim 12 , wherein the first and second comparator are configured to receive a feedback signal based on the switched drive signal.
18. The switched driver circuit according to claim 12 , wherein the switched drive circuit is a switched constant current drive circuit.