Non volatile memory
View Patent ↗An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.
1. A non-volatile semiconductor memory comprising:
one or more non-volatile memories;
a capacitor; and
a controller,
wherein a power-supply voltage of a first level is supplied from an external source,
wherein said capacitor is coupled to said external source,
wherein said controller issues an operation command making a request for a read operation, a write operation or an erase operation to said non-volatile memory,
wherein said non-volatile memory has a plurality of memory cells and carries out an operation in accordance with an operation command received from said controller,
wherein, in a read operation, said nonvolatile memory carries out an operation to read data from said memory cells particularly pertaining to a first group and outputs said data to said controller,
wherein, in a write operation, said non-volatile memory carries out an operation to receive data from said controller and writes said data into said memory cells particularly pertaining to said first group,
wherein, in an erase operation, said non-volatile memory carries out an operation to erase data from said memory cells particularly pertaining to said first group, and
wherein, when if a drop of said power-supply voltage to a second level lower than said first level is detected in the course of said write or erase operation, said non-volatile memory discontinues said write or erase operation currently being executed and carries out a first operation, for writing information to a memory cell coupled to a same word line as was selected for said write or erase operation, using electric charge in said capacitor to supply power for said first operation.
2. A non-volatile semiconductor memory according to claim 1 ,
wherein said memory cells each have a threshold voltage, and a write or erase operation carried out on a specific one of said memory cells shifts said threshold voltage of said specific memory cell to a distribution range of one among a plurality of threshold voltage distributions,
wherein said erase operation carried out on said particular memory cells pertaining to said first group shifts said threshold voltage of each of said particular memory cells to a distribution range of a specific one of said threshold voltage distributions, which indicates a state of erased data,
wherein in said erase operation to shift said threshold voltage of each of said particular memory cells to said distribution range of said specific threshold voltage distribution indicating said state of erased data, said threshold voltages of a specific one or more of said particular memory cells may inadvertently go beyond said distribution range of said specific threshold voltage distribution indicating said state of erased data, and
wherein said first operation is carried out to bring back said threshold voltages of said specific one or more of said particular memory cells to said distribution range of said specific threshold voltage distribution indicating said state of erased data.
3. A non-volatile semiconductor memory according to claim 2 , wherein, in said write operation, an erase operation is performed, and then said threshold voltage of each of said particular memory cells is shifted to a distribution range of one of said threshold voltage distributions in accordance with data to be stored in each of said particular memory cells.
4. A non-volatile semiconductor memory according to claim 1 ,
wherein each of said one or more non-volatile memories has a plurality of word lines,
wherein said memory cells particularly pertaining to said first group are connected to one of said word lines, which is also connected to special memory cells pertaining to a second group, and
wherein said first operation is carried out also to store information indicating the fact that said power-supply voltage has dropped to said second level into said special memory cells pertaining to said second group.
5. A non-volatile semiconductor memory according to claim 4 , wherein, if said information indicating the fact that said power-supply voltage has dropped to said second level is found stored in said special memory cells pertaining to said second group in said read operation, a read error is reported to said controller.