Semiconductor memory device comprising controllable threshould voltage dummy memory cells
The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block and a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliable operation.
1. A semiconductor memory device comprising:
a memory block in which memory cell units obtained by connecting plural memory cells are arranged in an array;
select transistors provided at a first side and a second side of the memory cell units;
three dummy word lines provided between the plural memory cells and the select transistor which is provided at the first side of the memory cell units and another three dummy word lines provided between the plural memory cells and the select transistor which is provided at the second side of the memory cell units; and
a word driver for controlling dummy word line potential of at least one of the dummy word lines.
2. The semiconductor memory device according to claim 1 ,
wherein the word driver for controlling the dummy word line potential of at least one of the dummy word lines is disposed in a word decoder.
3. The semiconductor memory device according to claim 1 , wherein a control signal of a word driver for controlling the dummy word line potential is commonly used as a control signal of a word driver for controlling another dummy word line potential.
4. The semiconductor memory device according to claim 1 , wherein a word driver for controlling the dummy word line potential simultaneously controls another dummy word line potential.
5. The semiconductor memory device according to claim 1 , wherein a word driver for controlling the dummy word line potential has the same configuration as that of a word driver for controlling a word line of a data storage area.
6. The semiconductor memory device according to claim 1 , wherein width of a dummy word line disposed on the outermost side of the memory cell unit is set to be wider than that of other dummy word lines.
7. The semiconductor memory device according to claim 1 , wherein in the memory cell unit, plural nonvolatile memory cells are connected in parallel.
8. The semiconductor memory device according to claim 1 , wherein the memory cell uses an inversion layer as a bit line in the memory cell unit.
9. The semiconductor memory device according to claim 7 , further comprising means which controls a threshold voltage so that a dummy memory cell formed just below each of the dummy word lines becomes nonconductive.
10. The semiconductor memory device according to claim 1 , wherein the memory cell unit is an NAND type EEPROM in which plural nonvolatile memory cells are connected in series.
11. The semiconductor memory device according to claim 10 , further comprising means which controls a threshold voltage so that a dummy memory cell formed just below each of the dummy word lines becomes conductive.
12. A semiconductor memory device comprising: a memory block in which memory cell units obtained by connecting plural memory cells are arranged in an array; two dummy word lines adjacent to a select transistor at each of both ends of the memory cell unit in a memory cell array constructed by disposing plural memory blocks; and a word driver for controlling at least one dummy word line potential in the dummy word lines, the word driver being provided in a word decoder.
13. The semiconductor memory device according to claim 12 , wherein a control signal of a word driver for controlling the dummy word line potential is commonly used as a control signal of a word driver for controlling another dummy word line potential.
14. The semiconductor memory device according to claim 12 , wherein a word driver for controlling the dummy word line potential simultaneously controls another dummy word line potential.
15. The semiconductor memory device according to claim 12 , wherein a word driver for controlling the dummy word line potential has the same configuration as that of a word driver for controlling a word line of a data storage area.
16. The semiconductor memory device according to claim 12 , wherein width of a dummy word line disposed on the outermost side of the memory cell unit is set to be wider than that of other dummy word lines.
17. The semiconductor memory device according to claim 12 , wherein in the memory cell unit, plural nonvolatile memory cells are connected in parallel.
18. The semiconductor memory device according to claim 12 , wherein the memory cell uses an inversion layer as a bit line in the memory cell unit.
19. The semiconductor memory device according to claim 17 , further comprising means which controls a threshold voltage so that a dummy memory cell formed just below the dummy word line becomes nonconductive.
20. The semiconductor memory device according to claim 12 , wherein the memory cell unit is an NAND type EEPROM in which plural nonvolatile memory cells are connected in series.
21. The semiconductor memory device according to claim 20 , further comprising means which controls a threshold voltage so that a dummy memory cell formed just below the dummy word line becomes conductive.