IP Library Granted Patent US 7,253,679
Granted Patent B2
US 7,253,679 · App. 11/225,188 · Granted Aug 7, 2007

Operational amplifier and method for canceling offset voltage of operational amplifier

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Quick Facts
Patent No.
US 7,253,679
App. No.
11/225,188
Granted
Aug 7, 2007
Kind
B2
Abstract

An operational amplifier that cancels offset voltage while enabling its gain to be set to any value. The operational amplifier includes a first switch for short-circuiting the gates of two transistors in a first differential input unit. A capacitor is connected to the gates of two transistors in a second differential input unit, which is connected in parallel to the first differential input unit. The capacitor holds offset voltage derived from output voltage generated by an operational amplifier circuit. The capacitor generates a potential difference between the gates of the transistors in the second differential input unit to cancel the offset voltage.

Claims (12)

1. An operational amplifier comprising:

an input terminal and an output terminal connected to the input terminal for outputting output voltage;

an operational amplifier circuit including a current mirror, having a first pair of transistors, and a first differential input unit, having a second pair of transistors connected to the current mirror;

an offset adjustment circuit including a second differential input unit having a third pair of transistors connected to the current mirror;

a first switch for switching between a first connection point, in which a gate of one of the second pair of transistors is connected to a gate of the other one of the second pair of transistors, and a second connection point, in which the gate of the one of the second pair of transistors is connected to the input terminal;

a second switch for switching between a connection state, in which a gate of one of the third pair of transistors is connected to the input terminal, and a disconnection state, in which the gate of the one of the third pair of transistors is disconnected from the input terminal; and

an offset voltage holding unit, connected to gates of the third pair of transistors, for holding an offset voltage derived from output voltage generated by the operational amplifier circuit when the first switch is switched to the first connection point and the second switch is switched to the connection state, the offset voltage holding unit generating a potential difference between the gates of the third pair of transistors in accordance with the held offset voltage when the first switch is switched to the second connection point and the second switch is switched to the disconnection state.

2. The operational amplifier according to claim 1 , wherein the offset voltage holding unit includes a capacitor connected between the gates of the third pair of transistors.

3. A method for canceling offset voltage derived from output voltage of an operational amplifier, wherein the operational amplifier includes an input terminal, an output terminal connected to the input terminal for outputting the output voltage, an operational amplifier circuit provided with a current mirror, having a first pair of transistors, and a first differential input unit, having a second pair of transistors connected to the current mirror, an offset adjustment circuit provided with a second differential input unit having a third pair of transistors connected to the current mirror, and an offset voltage holding unit connected to gates of the third pair of transistors for holding the offset voltage, the method comprising:

holding the offset voltage with the offset voltage holding unit by connecting a gate of one of the second pair of transistors to a gate of the other one of the second pair of transistors and connecting a gate of one of the third pair of transistors to the input terminal; and

generating a potential difference between the gates of the third pair of transistors in accordance with the held offset voltage to cancel the offset voltage by connecting the gate of the one of the second pair of transistors to the input terminal and disconnecting the gate of the one of the third pair of transistors from the input terminal.

4. The method according to claim 3 , wherein the offset voltage holding unit includes a capacitor connected between the gates of the third transistors, and said holding the offset voltage includes holding the offset voltage with the capacitor.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036038/0620 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021998/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2005
From: NISHIMORI, EIJI
To: FUJITSU LIMITED
Reel/Frame 016983/0066 →