Low frequency clock generation
View Patent ↗A first and a second resonator are fabricated monolithically adjacent to one another. The first resonator is the reference resonator. The resonant frequency of the second resonator is offset by a difference frequency Fo from the first resonator. Each resonator is included within an oscillator. A mixer receives the output of both oscillators. A low pass filter receives the mixer output and generates a clock signal whose frequency is equal to the difference frequency Fo.
1. A clock generation circuit comprising:
a first oscillator including a resonator having a first resonant frequency, having an oscillator output;
a second oscillator including a resonator having a second resonant frequency, having an oscillator output;
wherein the first and second resonant frequencies are separated by a difference frequency;
a mixer, receiving each of the oscillator outputs, generating a mixer output signal;
a low pass filter, receiving the mixer output signal, generation a clock signal that is proportional to the difference frequency;
a first register storing a preferred oscillator setting; and
a second register storing a temperature compensation setting;
one of the first and the second oscillators being adjustable by the preferred oscillator setting, and
the one of the first and the second oscillators being adjustable by the temperature compensation setting.
2. A clock generation circuit, as defined in claim 1 , wherein the resonators are selected from a group that includes film bulk acoustic resonators.
3. A clock generation circuit, as defined in claim 1 , further comprising a substrate that integrates the first and second oscillators, mixer, and low pass filter.
4. A clock generation circuit, as defined in claim 1 , wherein the resonators are selected from a group that includes film bulk acoustic resonators.
5. A clock generation circuit, as defined in claim 1 , wherein the other of the first and the second oscillators is adjustable by at least one of the preferred oscillator setting and the temperature compensation setting.
6. A clock generation circuit, as defined in claim 5 , wherein one of the first and the second oscillators is adjustable by a modulation source.
7. A device comprising:
a substrate; and
a clock generation circuit, positioned proximate to the substrate, including,
a first oscillator including a resonator having a first resonant frequency, having an oscillator output,
a second oscillator including a resonator having a second resonant frequency, having an oscillator output,
wherein the first and second resonant frequencies are separated by a difference frequency,
a mixer, receiving each of the oscillator outputs, generating a mixer output signal,
a low pass filter, receiving the mixer output signal, generation a clock signal that is proportional to the difference frequency;
a first register storing a preferred oscillator setting; and
a second register storing a temperature compensation setting,
one of the first and the second oscillators being adjustable by the preferred oscillator setting, and
the one of the first and the second oscillators being adjustable by the temperature compensation setting.
8. A device, as in claim 7 , wherein the clock generation circuit is monolithically integrated in the substrate.
9. A device, as in claim 7 , wherein the clock generation circuit is attached to the substrate using flip chip technology.
10. A device, as in claim 7 , wherein the clock generation circuit is attached to the substrate using die stacking technology.
11. A device, as in claim 7 , wherein the clock generation circuit is adjacent to the substrate using a common leadframe.
12. A device, as defined in claim 7 , wherein the other of the first and the second oscillators is adjustable by at least one of the preferred oscillator setting and the temperature compensation setting.
13. A device, as defined in claim 12 , wherein one of the first and the second oscillators is adjustable by a modulation source.
14. A clock generation circuit comprising:
a first oscillator including a resonator having a first resonant frequency, having an oscillator output;
a second oscillator including a resonator having a second resonant frequency, having an oscillator output;
wherein the first and second resonant frequencies are separated by a difference frequency;
a mixer, receiving each of the oscillator outputs, generating a mixer output signal;
a low pass filter, receiving the mixer output signal, generating a clock signal that is proportional to the difference frequency;
a first register storing a preferred oscillator setting; and
one of the first and the second oscillators being adjustable by the preferred oscillator setting,
wherein the preferred oscillator setting comprises a selected oscillator frequency offset setting.
15. A clock generation circuit comprising:
a first oscillator including a resonator having a first resonant frequency, having an oscillator output;
a second oscillator including a resonator having a second resonant frequency, having an oscillator output;
wherein the first and second resonant frequencies are separated by a difference frequency;
a mixer, receiving each of the oscillator outputs, generation a mixer output signal;
a low pass filter, receiving the mixer output signal, generating a clock signal that is proportional to the difference frequency;
a first register storing a preferred oscillator setting; and
one of the first and the second oscillators being adjustable by the preferred oscillator setting,
wherein at least one of the first and second oscillators is a voltage controlled oscillator (VCO) and wherein at least one of the first and second resonant frequencies is adjustable by the preferred oscillator setting to cause the difference frequency to be a selected value.
16. A device comprising:
a substrate; and
a clock generation circuit, positioned proximate to the substrate, including,
a first oscillator including a resonator having a first resonant frequency, having and oscillator output,
a second oscillator including a resonator having a second resonant frequency, having an oscillator output,
wherein the first and second resonant frequencies are separated by a difference frequency,
a mixer, receiving each of the oscillator outputs, generation a mixer output signal,
a low pass filter, receiving the mixer output signal, generation a clock signal that is proportional to the difference frequency;
a first register storing a preferred oscillator setting; and
one of the first and the second oscillators being adjustable by the preferred oscillator setting,
wherein the preferred oscillator setting comprises a selected oscillator frequency offset setting.
17. A device comprising:
a substrate; and
a clock generation circuit, positioned proximate to the substrate, including,
a first oscillator including a resonator having a first resonant frequency, having an oscillator output,
a second oscillator including a resonator having a second resonant frequency, having an oscillator output,
wherein the first and second resonant frequencies are seperated by a difference frequency,
a mixer, receiving each of the oscillator outputs, generating a mixer output signal,
a low pass filter, receiving the mixer output signal, generating a clock signal that is proportional to the difference frequency;
a first register storing a preferred oscillator setting; and
one of the first and the second oscillators being adjustable by the preferred oscillator setting,
wherein at least one of the first and second oscillators is a voltage controlled oscillator (VCO) and wherein at least one of the first and second resonant frequencies is adjustable by the preferred oscillator setting to cause the difference frequency to be a selected value.