Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions
View Patent ↗Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.
1. A method of forming a pn junction diode in an integrated circuit, the method comprising:
forming a first region of relatively thick material on the surface of a substrate of a first conductivity type, wherein the first region of relatively thick material is thick enough to mask a selected implant;
forming a second region of relatively thick material on the surface of a substrate a predetermined distance from the first region, wherein the second region of relatively thick material is thick enough to mask a selected implant;
implanting high density of dopants of a second conductivity type in the substrate to form a diode contact using first edges of the first and second regions as masks to define edges of the diode contact, wherein the diode contact is positioned between the first and second regions; and
implanting dopants of a first conductivity type in the substrate to form first and second top gate regions using second edges of the first and second regions as masks to define first edges of the first and second top gate regions, wherein the distance between the diode contact and the first top gate region is defined by the lateral length of the first region and the distance between the diode contact and the second top gate region is defined by the lateral length of the second region.
2. The method of claim 1 , further comprising:
implanting high density dopants of the first conductivity type in the substrate to form at least one substrate contact region.
3. The method of claim 1 , further comprising:
implanting dopant of the second conductivity type in the substrate to form drift regions; and
diffusing the dopant of the second conductivity type that forms the drift regions so that the drift regions overlap under a respective one of the first and second regions to form a single main drift region.
4. The method of claim 1 , wherein the first and second regions are formed with gate material.
5. The method of claim 1 , wherein the first region is coupled to the second region, further wherein the first and second regions form a central opening defining the diode contact.
6. The method of claim 5 , wherein the first and second top gate regions extend around an outer perimeter of the first and second regions.
7. The method of claim 1 , wherein the first and second regions are formed with dielectric material.
8. The method of claim 7 , wherein the first and second regions are formed by local oxidation.