Clock generating circuit and clock generating method

1. A clock generating circuit which uses a reference clock as an input and carries out spectrum spread of an output clock in compliance with a modulating signal, comprising:

a phase comparator unit for comparing a phase difference between the reference clock and an internal clock or a divided internal clock, and outputting a phase difference signal in response to the result of comparison;

a clock generating unit for generating an output clock in response to the phase difference signal;

a phase difference signal modulating unit for modulating the phase difference signal in compliance with the modulating signal, and for outputting a phase difference modulating signal; and

a delay unit for delaying the output clock in compliance with the phase difference modulating signal; and for outputting the internal clock.

2. The clock generating circuit according to claim 1 , wherein the delay unit varies the delay time without any step when delaying the output clock.

3. The clock generating circuit according to claim 1 , wherein the delay unit includes a first delay element for generating delay time of the output clock signal, and the clock generating unit includes a second delay element for generating delay time equivalent to a half cycle of the output clock signal, and the first delay element and the second delay element are composed of elements of the same device structure.

4. The clock generating circuit according to claim 3 , wherein the delay time of the delay unit has the time equivalent to one cycle of the clock signal as the maximum delay time, and is modulated so as not to exceed the maximum delay time in compliance with the phase difference modulating signal.

5. The clock generating circuit according to claim 3 , wherein the second delay element is composed of one or a plurality of unit delay element(s), the first delay element is composed of the unit delay elements two times the second delay element, and the phase difference modulating signal is a bias signal of the first delay element, and is generated with the bias signal to the second delay element used as the maximum delay condition.

6. The clock generating circuit according to claim 5 , wherein the unit delay element includes a transfer gate, and the bias voltage to the transfer gate is modulated based on the phase difference signal or the phase difference modulating signal.

7. The clock generating circuit according to claim 1 , wherein the phase comparator unit outputs the phase difference signal whose current value changes, the clock generating unit generates the output clock in compliance with a current value of the inputted phase difference signal, the phase difference signal modulating unit outputs a phase difference modulating signal whose current value changes, and the delay unit has the delay time of the output clock varied in compliance with the current value of the inputted phase difference modulating signal.

8. The clock generating circuit according to claim 1 , including a modulation control unit for outputting the modulation signal at a timing in response to the internal clock or the divided internal clock inputted into the phase comparator unit.

9. A clock generating method for carrying out spectrum spread of an output clock in compliance with a modulating signal using a reference clock as an input, comprising the steps of:

comparing a phase difference between the reference clock and an internal clock or the divided internal clock, and outputting a phase difference signal in response to the result of comparison;

generating an output clock in response to the phase difference signal;

modulating the phase difference signal in compliance with the modulating signal, and outputting a phase difference modulating signal; and

delaying the output clock in compliance with the phase difference modulating signal, and for outputting the internal clock.

10. The clock generating method according to claim 9 , wherein, in the step of outputting the internal clock, the delay time changes without any step when delaying the output clock.

11. The clock generating method according to claim 9 , wherein the delay time of the step of outputting the internal clock is modulated so as not to exceed the maximum delay time in compliance with the phase difference modulating signal with the same time as one cycle of the clock signal used as the maximum delay time.

12. The clock generating method according to claim 9 , wherein the step of outputting the phase difference signal outputs the phase difference signal whose current value changes in compliance with the result of comparison;

the step of generating the output clock generates the output clock in compliance with the current value of the inputted phase difference signal;

the step of outputting the phase difference modulating signal outputs a phase difference modulating signal whose current value changes in compliance with the modulating signal; and

the step of outputting the internal clock, the delay time of the output clock changes in compliance with the current value of the inputted phase difference modulating signal.

13. The clock generating method according to claim 9 , including the step of outputting the modulation signal at a timing in response to the internal clock or the divided internal clock inputted in the step of outputting the phase difference signal.