IP Library Granted Patent US 7,501,898
Granted Patent B2
US 7,501,898 · App. 11/271,074 · Granted Mar 10, 2009

Method and apparatus for generating an optimized reference current threshold

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,501,898
App. No.
11/271,074
Granted
Mar 10, 2009
Kind
B2
Abstract

In one embodiment, apparatus is provided with current optimization logic, a programmable current source for generating a reference current threshold, and current programming logic. In response to a plurality of input pulses received by a first TIA, the current optimization logic produces a series of digitized current values in response to i) a signal correlated to an output of the first TIA, to ii) a reference signal to which the output of the first TIA is compared. The current programming logic i) programs the programmable current source using ones of the series of digitized current values, until a predetermined condition is met, and then ii) locks the programmable current source to a most recent one of the digitized current values. In response to the reference current threshold, a second TIA produces the reference signal.

Claims (32)

1. Apparatus, comprising:

current optimization logic to, in response to a plurality of input pulses received by a first transimpedance amplifier (TIA), produce a series of digitized current values in response to comparisons of i) a signal correlated to an output of the first TIA, to ii) a reference signal to which the output of the first TIA is compared;

a programmable current source for generating a reference current threshold;

current programming logic to i) program the programmable current source using ones of the series of digitized current values, until a predetermined condition is met, and then ii) lock the programmable current source to a most recent one of the digitized current values; and

a second TIA to, in response to the reference current threshold generated by the programmable current source, produce the reference signal.

2. The apparatus of claim 1 , wherein the first TIA comprises a feedback resistor; and wherein the signal correlated to the output of the first TIA is a signal derived from a tap of the feedback resistor.

3. The apparatus of claim 1 , wherein the signal correlated to the output of the first TIA is a primary output of the first TIA.

4. The apparatus of claim 1 , wherein the current optimization logic comprises:

a first comparator to, in response to the plurality of input pulses, compare i) the signal correlated to the output of the first TIA, to ii) the reference signal; and

a first counter that is incremented in response to pulses of the output of the first TIA, wherein values of the first counter provide the series of digitized current values.

5. The apparatus of claim 4 , further comprising a second counter that is incremented in response to pulses of the output of the first TIA; wherein said predetermined condition is a predetermined count of the second counter.

6. The apparatus of claim 4 , further comprising a second comparator receiving i) the output of the first TIA, and ii) the reference signal.

7. The apparatus of claim 6 , further comprising logic to generate said predetermined condition when an output of the second comparator is de-asserted faster than the output of the first comparator.

8. The apparatus of claim 4 , wherein the current programming logic further comprises one-time programmable logic to store the digitized current value to which the programmable current source is locked.

9. The apparatus of claim 1 , wherein the current optimization logic comprises a counter, and wherein the predetermined condition is a predetermined count of the counter.

10. The apparatus of claim 9 , wherein the counter is incremented in response to pulses of the output of the first TIA.

11. The apparatus of claim 1 , wherein the current programming logic further comprises one-time programmable logic to store the digitized current value to which the programmable current source is locked.

12. The apparatus of claim 1 , further comprising a common semiconductor substrate on which the current optimization logic, the programmable current source and the current programming logic are formed.

13. The apparatus of claim 1 , further comprising a photosensor, coupled to an input of the first TIA.

14. A method for optimizing a reference current threshold of an opto-coupler, comprising:

in response to a plurality of input pulses received by a transimpedance amplifier (TIA) of the opto-coupler, producing a series of digitized current values in response to comparisons of i) a signal correlated to an output of the TIA, to ii) a reference signal to which the output of the TIA is compared;

until a predetermined condition is met, programming a programmable current source using ones of the series of digitized current values, the programmable current source generating the reference current threshold;

after the predetermined condition is met, locking the programmable current source to a most recent one of the digitized current values; and

in response to the reference current threshold generated by the programmable current source, producing the reference signal.

15. The method of claim 14 , further comprising, deriving the signal correlated to the output of the TIA from a tap of a feedback resistor of the TIA.

16. The method of claim 14 , wherein the series of digitized current values is produced by,

in response to the plurality of input pulses, comparing i) the signal correlated to the output of the TIA, to ii) the reference signal; and

in response to said comparisons resulting in a predetermined outcome, incrementing a count; wherein values of the count provide the series of digitized current values.

17. The method of claim 14 , further comprising:

counting pulses of the output of the TIA; and

generating said predetermined condition in response to a predetermined count of said pulses.

18. The method of claim 14 , further comprising, storing the digitized current value to which the programmable current is locked in one-time programmable logic.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2006
From: CHOW, FUN KOK
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 017138/0070 →