IP Library Patent Application 11314569
Patent Application
App. No. 11/314,569

Systems and methods for designing integrated circuits

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
11/314,569
Abstract

Systems and methods for designing integrated circuits (ICs) are provided. A representative method includes: providing a netlist; determining components required to implement test of at least a portion of the integrated circuit defined by the netlist; provide a revised netlist including the components determined; and performing a place and route operation with respect to the revised netlist.

Claims (34)

1 . A method for designing an integrated circuit (IC), said method comprising:

providing a netlist;

determining components required to implement test of at least a portion of the integrated circuit defined by the netlist;

providing a revised netlist including the components determined; and

performing a place and route operation with respect to the revised netlist.

2 . The method of claim 1 , wherein providing a netlist comprises generating a synthesized netlist.

3 . The method of claim 1 , wherein determining components comprises:

determining a number of flip-flops corresponding to the portion of the IC;

applying at least a first scan methodology to the portion of the IC; and

determining additional components required to implement the first scan methodology.

4 . The method of claim 1 , wherein determining components comprises organizing flip-flops into a plurality of scan chains of desired lengths.

5 . The method of claim 1 , wherein determining components comprises adding scan input and scan output ports to the netlist.

6 . The method of claim 1 , wherein determining components comprises adding flip-flops to alter scan chain lengths.

7 . The method of claim 1 , wherein determining components comprises altering at least one of hierarchy, circuitry, wiring, and connections with respect to the netlist.

8 . The method of claim 1 , wherein performing place and route functionality comprises ensuring that IC design criteria associated with timing, area and power requirements are satisfied.

9 . The method of claim 1 , wherein determining components is performed prior to performing a place and route operation of the IC.

10 . The method of claim 1 , wherein determining components is performed prior to placement but further specification of component interconnection is performed after placement and before routing.

11 . An integrated circuit formed by the method of claim 1 .

12 . A computer-readable medium having stored thereon information for performing a computer-implemented method, the method comprising:

providing a netlist;

determining components required to implement test of at least a portion of the integrated circuit defined by the netlist;

providing a revised netlist including the components determined; and

performing a place and route operation with respect to the revised netlist.

13 . A system for designing an integrated circuit (IC), said system comprising:

a processor operative to execute instructions; and

a memory communicating with the processor and storing instructions for:

providing a netlist;

determining components required to implement test of at least a portion of the integrated circuit defined by the netlist;

providing a revised netlist including the components determined; and

performing a place and route operation with respect to the revised netlist.

14 . The system of claim 13 , further comprising:

means for outputting the revised netlist.

15 . The system of claim 13 , further comprising:

a display device communicating with the processor and operative to output the revised netlist.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2007
From: BRATT, JOHN; WILLIAMS, BRETT; REARICK, JEFFREY
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 019975/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD
Reel/Frame 017675/0001 →