IP Library Granted Patent US 7,548,699
Granted Patent B2
US 7,548,699 · App. 11/316,033 · Granted Jun 16, 2009

Channel-length modulation (CLM) compensation method and apparatus

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Quick Facts
Patent No.
US 7,548,699
App. No.
11/316,033
Granted
Jun 16, 2009
Kind
B2
Abstract

A power supply generates a supply voltage that varies from a first voltage level to a second voltage level. A first current source is coupled to the power supply and generates a current that varies due to channel-length modulation. A channel-length modulation (CLM) compensation mechanism is provided to reduce the current variation of the first current source by compensating the channel-length modulation (CLM) of the first current source.

Claims (29)

1. An optocoupler system, comprising:

a light source that when driven by a drive signal is configured to generate light;

a first current source coupled to the light source and coupled to a voltage that varies, the drive signal varying in response to the changing voltage due to channel length modulation;

a channel length modulation compensation mechanism coupled to the first current source and configured to reduce the variation in the drive signal of the first current source caused by the channel length modulation of the current source, the channel length modulation mechanism comprising first and second current mirrors, a voltage source, and a resistor, the resistor having a value based on the expression: 1/(delta Y/delta X), wherein delta Y is the difference between a second drain current of the second current mirror and a first drain current of the first current mirror, and delta X is the difference between a second drain to source voltage of the second current mirror and a first drain to source voltage of the first current mirror.

2. The system of claim 1 , wherein the variation between the first drain to source voltage and the second drain to source voltage is more than about 10 percent (10%).

3. The system of claim 1 , wherein the voltage source comprises diodes.

4. The system of claim 1 , wherein:

the first current mirror has a 1:N ratio;

the second current mirror has a 1:M ratio;

and N and M can be adjusted to any real value.

5. The system of claim 1 , wherein the channel length modulation compensation mechanism further comprises:

a second fixed current source operably coupled to the first current mirror and the second current mirror.

6. The system of claim 5 , wherein the second fixed current source is a cascade current source.

7. The system of claim 1 , wherein the channel length modulation begins when the voltage is equal to about 3 volts.

8. The system of claim 1 , wherein the channel length modulation compensation mechanism is configured to reduce the variation of the drive signal due to channel length modulation by more than about 10 percent (10%).

9. A system, comprising:

a power supply configured to generate a supply voltage that varies from a first voltage level to a second voltage level;

a first current source operably coupled to the power supply and configured to generate a current that varies due to channel-length modulation; and

a channel-length modulation (CLM) compensation mechanism, operably coupled to the first current source, and configured to reduce the current variation of the first current source by compensating the channel-length modulation (CLM) of the first current source, the channel length modulation mechanism comprising first and second current mirrors, a voltage source, and a resistor, the resistor having a value based on the expression: 1/(delta Y/delta X), wherein delta Y is the difference between a second drain current of the second current mirror and a first drain current of the first current mirror, and delta X is the difference between a second drain to source voltage of the second current mirror and a first drain to source voltage to the first current mirror.

10. The system of claim 9 , wherein the channel length modulation compensation mechanism further comprises a second fixed current source operably coupled to the first current mirror and the second current mirror.

11. The system of claim 10 , wherein the second fixed current source is a cascode current source.

12. The system of claim 9 , wherein:

the first current mirror has a 1:N ratio;

the second current mirror has a 1:M ratio;

and N and M can be adjusted to any real value.

13. The system of claim 9 , wherein

the voltage source is operably coupled to the second current mirror.

14. The system of claim 9 , wherein the variation between the first drain to source voltage and the second drain to source voltage is more than about 10 percent (10%).

15. The system of claim 9 , wherein the voltage source comprises diodes.

Assignments (12)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
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From: AGILENT TECHNOLOGIES, INC.
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
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PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD
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From: LEE, KAH WENG; ZHANG, BIN
To: AGILENT TECHNOLOGIES, INC.
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