Semiconductor memory device and semiconductor integrated circuit device
View Patent ↗A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
1. A semiconductor integrated circuit, comprising:
a central processing unit; and
a memory unit,
wherein said central processing unit is operable to access said memory unit,
wherein said memory unit includes a memory mat, a first control circuit, a second control circuit, a first power controller, and a second power controller,
wherein said memory mat is operable to store data from said central processing unit,
wherein said first control circuit controls said memory mat based on an address from said central processing unit,
wherein said second control circuit is operable to output said data from said memory mat to said central processing unit,
wherein said first power controller is operable to control a power supply for said first control circuit,
wherein said second power controller is operable to control a power supply for said first power controller,
wherein said first power controller provides said power supply to said first control circuit and said second control circuit when said memory unit is accessed from said central processing unit, and
wherein said first power controller stops said power supply for said first control circuit when said memory mat is un-selected.
2. A semiconductor integrated circuit according to claim 1 ,
wherein said second power controller is operable to stop said power supply to said first power controller when said memory unit is un-selected.
3. A semiconductor integrated circuit according to claim 1 ,
wherein said memory unit further includes a second memory mat, a third control circuit, a fourth control circuit, and a third power controller, and
wherein said third power controller is operable to control a power supply to said third control circuit.
4. A semiconductor integrated circuit according to claim 3 ,
wherein said second power controller is operable to control said power supply of said first power controller and said third power controller.
5. A semiconductor integrated circuit according to claim 3 ,
wherein said third power controller is operable to stop said power supply to third control circuit when said first memory mat is selected.
6. A semiconductor integrated circuit according to claim 3 ,
wherein each of said first and third control circuits includes a word driver, and
wherein each of said second and fourth control circuits includes an output circuit.
7. A semiconductor integrated circuit according to claim 1 ,
wherein said second power controller outputs a control signal to said first and third power controllers when said second power controller has inputted a standby signal.
8. A semiconductor integrated circuit according to claim 7 ,
wherein said first power controller shuts off a power supply based on said control signal.