Microcomputer and microprocessor having flash memory operable from single external power supply
View Patent ↗A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.
1. A semiconductor processing device comprising:
a nonvolatile memory unit;
a voltage generating unit; and
a first terminal,
wherein said nonvolatile memory unit, said voltage generating unit, and said first terminal are formed on one semiconductor substrate,
wherein said voltage generating unit is adapted to generate a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and is adapted to provide said first voltage to said nonvolatile memory unit for storing data therein,
wherein said first terminal is adapted to provide said first voltage generated by said voltage generating unit to outside of the semiconductor processing device, and
wherein said first voltage provided to outside of the semiconductor processing device via said first terminal is adapted to permit checking a voltage level of the first voltage and correcting said voltage level of the first voltage in accordance with predetermined parameters.
2. A semiconductor processing device according to claim 1 ,
wherein the voltage level of said first voltage is higher than a voltage level of said operation voltage.
3. A semiconductor processing device according to claim 1 ,
wherein said nonvolatile memory unit includes a first area to store user data and a second area to store information adapted to be used for correcting a voltage level of said first voltage in accordance with predetermined parameters.
4. A semiconductor processing device comprising:
a nonvolatile memory unit;
a voltage generating unit; and
a first terminal,
wherein said voltage generating unit is adapted to generate a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and is adapted to provide said first voltage to said nonvolatile memory unit for storing data therein,
wherein said first terminal is adapted to provide said first voltage generated by said voltage generating unit to outside of the semiconductor processing device, and
wherein said first voltage provided to outside of the semiconductor processing device via said first terminal is adapted to permit checking a voltage level of the first voltage and correcting said voltage level of the first voltage in accordance with predetermined parameters,
wherein said voltage generating unit is adapted to generate a second voltage, a voltage level of which is lower than a voltage level of said operation voltage, and is adapted to generate said first voltage from said second voltage.
5. A semiconductor processing device according to claim 4 wherein said operation voltage is one of a third voltage and a fourth voltage, the voltage level of which is lower than a voltage level of said third voltage.
6. A semiconductor processing device according to claim 5 , further comprising a central processing unit for accessing to said nonvolatile memory unit.
7. A semiconductor processing device according to claim 4 ,
wherein said nonvolatile memory unit, said voltage generating unit, and said first terminal are formed on one semiconductor substrate.
8. A semiconductor processing device comprising:
a nonvolatile memory unit;
a voltage generating unit; and
a first terminal.
wherein said voltage generating unit is adapted to generate a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and is adapted to provide said first voltage to said nonvolatile memory unit for storing data therein,
wherein said first terminal is adapted to provide said first voltage generated by said voltage generating unit to outside of the semiconductor processing device, and
wherein said first voltage provided to outside of the semiconductor processing device via said first terminal is adapted to permits permit checking a voltage level of the first voltage and correcting said voltage level of the first voltage in accordance with predetermined parameters,
wherein said nonvolatile memory unit includes a first area to store user data and a second area to store information to be used for correcting a voltage level of said first voltage in accordance with predetermined parameters,
wherein, in response to an initialization operation of the semiconductor processing device, said information stored in said second area of said nonvolatile memory unit is read out and is stored into a register, and
wherein said voltage generating unit is adapted to generate said first voltage in accordance with said information stored in said register.
9. A semiconductor processing device according to claim 8 ,
wherein said voltage generating unit is adapted to generate a fifth voltage generated from said operation voltage and is adapted to provide said fifth voltage to said nonvolatile memory unit for data erasing, and
wherein said first terminal is adapted to provide said fifth voltage to outside of the semiconductor device.
10. A semiconductor processing device according to claim 9 ,
wherein said information stored in said second area of said nonvolatile memory unit permits correcting a voltage level of said fifth voltage.
11. A semiconductor processing device according to claim 8 ,
wherein said nonvolatile memory unit, said voltage generating unit, and said first terminal are formed on one semiconductor substrate.