Semiconductor device
View Patent ↗Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p − type semiconductor region and p − type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n − type single crystal silicon layer 1 B is ρ (Ω·cm) the CHSP is sets to satisfy the following equation: CHSP≦3.80+0.148ρ.
1. A semiconductor device having a trench gate type MISFET formed on a semiconductor substrate, comprising:
a plurality of first grooves extending in a first direction on the semiconductor substrate, said first grooves being connected with each other;
a second groove extending in a second direction on the semiconductor substrate, said second direction crossing the first direction, and said second groove being connected with the first grooves;
a plurality of gate electrodes of the trench gate type MISFET formed in the first grooves respectively, said gate electrodes being connected with one another;
a gate extraction electrode formed in the second groove, said gate extraction electrode being connected with the gate electrode;
an insulating film formed over the gate electrode and the gate extraction electrode;
a contact groove formed in the insulating film, said contact groove reaching an upper surface of the gate extraction electrode; and
a gate line formed over the insulating film, said gate line being electrically connected with the gate extraction electrode,
wherein each of terminal portions of the first grooves connects with the second groove; and
each of terminal portions of the gate electrodes connects with the gate extraction electrode; and
the contact groove is located directly above the second groove.
2. A semiconductor device according to claim 1 , wherein a portion of the gate line is formed in the contact groove, and
the gate extraction electrode contacts with the gate line formed in the contact groove.
3. A semiconductor device according to claim 1 , wherein a gate pad is formed over the semiconductor substrate, and
the gate line is electrically connected with the gate pad.
4. A semiconductor device according to claim 1 , wherein the gate extraction electrode is disposed around the MISFET on a main surface of the semiconductor substrate.
5. A semiconductor device according to claim 1 , wherein the gate electrode and the gate extraction electrode are comprised of a polycrystalline silicon film.
6. A semiconductor device according to claim 1 , wherein the gate line is comprised of an aluminum film.
7. A semiconductor device according to claim 1 , wherein the first and second grooves are formed in an identical process; and
the gate electrode of the trench gate type MISFET and the gate extraction electrode are formed in an identical process.