Self-compensating mark design for stepper alignment
View Patent ↗A system and method for fabricating integrated circuits using four fine alignment targets per stepper shot. The four alignment targets are disposed within the scribe line on each side of a four-sided stepper shot. The targets on opposites sides of the region are located in mirror-image positions. For example, in a square or rectangular region, the targets could be at the mid-point of each side, or at each corner. Because the scribe lines for adjoining stepper shots overlap, a target in one shot will overlay a target from a preceding shot. In a positive resist process, for example, the target resulting from the overlay will be reduced in size by an amount corresponding to the amount of rotational error, if any. However, the target will still indicate the center of the stepper shot, thereby compensating for the rotational error with no further measurements.
1. A reticle used to form alignment targets on a wafer, said reticle comprising:
a four-sided region comprising a first pattern for forming an integrated circuit on said wafer, said region having a scribe line along its perimeter; and
a second pattern disposed within said scribe line and comprising four alignment target patterns for forming four alignment targets on said wafer in a stepper shot; wherein one alignment target pattern is located on each side of said region, and
wherein an alignment target pattern on a first side of said region and an alignment target pattern on a second side of said region opposing said first side provide respective alignment targets in mirror image positions.
2. The reticle as recited in claim 1 wherein opposing sides of said region are equal in length, and wherein each of said alignment target patterns is located at a mid-point of a side of said region.
3. The reticle as recited in claim 1 wherein each of said four alignment target patterns is located at a corner of said region.
4. The reticle as recited in claim 1 wherein said alignment target patterns result from use of a plurality of rectangular-shaped masks.
5. The reticle as recited in claim 1 wherein said alignment target patterns are configured to form said alignment targets according to a positive resist process.
6. The reticle as recited in claim 1 wherein said alignment target patterns are configured to form said alignment targets according to a negative resist process.
7. The reticle as recited in claim 1 , wherein for adjoining stepper shots on said wafer further including another four-sided region having a scribe line along its perimeter and therewithin first and second alignment target patterns located on opposing sides wherein for the adjoining stepper shots adjacent alignment target patterns are configured for overlaying alignment targets formed therefrom.
8. The reticle as recited in claim 7 , wherein the first and second alignment target patterns of the respective four-sided regions are configured to provide the alignment target overlay for adjoining stepper shots to compensate for rotational error of the reticle.
9. The reticle as recited in claim 8 , for adjoining stepper shots on said wafer, further including another four-sided region having a scribe line along its perimeter and therewithin first and second alignment target patterns located on opposing sides, wherein the alignment target patterns of the four-sided regions are configured to form said alignment targets according to a positive resist process.
10. The reticle as recited in claim 1 , for adjoining stepper shots on said wafer, further including another four-sided region having a scribe line along its perimeter and therewithin first and second alignment target patterns located on opposing sides, wherein the alignment target patterns of the four-sided regions are configured to form said alignment targets according to a negative resist process.
11. The reticle as recited in claim 1 , wherein the alignment target patterns having respective alignment targets in mirror image positions are configured such that each alignment target of one of the respective alignment target patterns is in a mirror image position relative to an alignment target of the other of the respective alignment target patterns.
12. The reticle as recited in claim 11 , wherein for adjoining stepper shots on said wafer further including another four-sided region having a scribe line along its perimeter and therewithin first and second alignment target patterns located on opposing sides wherein for the adjoining stepper shots adjacent alignment target patterns are configured for overlaying alignment targets formed therefrom.
13. The reticle as recited in claim 11 , wherein for adjoining stepper shots on said wafer further including another four-sided region having a scribe line along its perimeter and therewithin first and second alignment target patterns located on opposing sides wherein for the adjoining stepper shots adjacent alignment target patterns are configured for overlaying alignment targets formed therefrom, and wherein the first and second alignment target patterns of the respective four-sided regions are configured to provide the alignment target overlay for adjoining stepper shots to compensate for rotational error of the reticle.