Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
1. A semiconductor device comprising:
a first MISFET and a vertical MISFET,
wherein the first MISFET is formed on a major surface of a semiconductor substrate,
wherein a metal film is formed over the first MISFET with an insulating film interposed therebetween,
wherein the vertical MISFET is formed over the metal film,
wherein a barrier metal layer is formed over the metal film, and
wherein the vertical MISFET is formed over the barrier metal layer and is electrically connected to the first MISFET through the metal film and the barrier metal film.
2. A semiconductor device according to claim 1 ,
wherein the barrier metal layer is comprised of a TiN film, and
wherein the metal layer is comprised of a W film.
3. A semiconductor device according to claim 1 ,
wherein the vertical MISFET is electrically connected to the metal layer via a throughhole such that the throughhole is formed inside of the barrier metal layer.
4. A semiconductor device according to claim 1 ,
wherein the vertical MISFET includes a source region, a channel forming region and a drain region each formed in a silicon film,
wherein the vertical MISFET includes a gate electrode formed on the silicon film through a gate insulating film,
wherein the insulating film includes an opening,
wherein a plug including metal material is formed in the opening, and
wherein the silicon film is electrically connected to the first MISFET through the barrier metal layer, the metal film and the plug.
5. A semiconductor device according to claim 1 ,
wherein a memory cell of a static random memory includes the first MISFET and the vertical MISFET serving as a driver MISFET and a load MISFET, respectively.
6. A semiconductor device comprising:
a first MISFET; and
a second MISFET,
wherein the first MISFET is formed on a major surface of a semiconductor substrate,
wherein a metal layer is formed over the first MISFET with an insulating film interposed therebetween,
wherein a barrier metal layer is formed over the metal layer, and
wherein the second MISFET is formed over the barrier metal layer and is electrically connected to the first MISFET through the metal layer and the barrier metal layer.
7. A semiconductor device according to claim 6 ,
wherein the second MISFET includes a source region, a channel forming region and a drain region each formed in a silicon film,
wherein the second MISFET includes a gate electrode formed on the silicon film through a gate insulating film,
wherein the insulating film includes an opening,
wherein a plug including a metal film is formed in the opening, and
wherein the silicon film is electrically connected to the first MISFET through a barrier metal layer, the metal layer and the plug.
8. a semiconductor device according to claim 7 ,
wherein the barrier metal layer includes a titanium nitride film, and
wherein the metal layer includes a tungsten film.
9. A semiconductor device according to claim 6 ,
wherein the second MISFET is a vertical MISFET.
10. A semiconductor device according to claim 6 ,
wherein a memory cell of a static random memory includes the first MISFET and the second MISFET serving as a driver MISFET and a load MISFET, respectively.