Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
View Patent ↗Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
1. A semiconductor memory device comprising:
a memory cell with a first drive MISFET and a second drive MISFET, a first transfer MISFET and a second transfer MISFET and a first load MISFET and a second load MISFET,
the drive MISFETs and the transfer MISFETs formed on a major surface of a semiconductor substrate such that a gate electrode of the first driver MISFET and a gate electrode of the first transfer MISFET extend over a first active region and such that a gate electrode of the second driver MISFET and a gate electrode of the second transfer MISFET extend over a second active region,
wherein the first active region extends in a first direction such that the gate electrode of the first driver MISFET and the gate electrode of the first transfer MISFET are arranged in the first direction and such that a gate length direction thereof is in parallel with the first direction,
wherein the second active region extends in the first direction such that the gate electrode of the second driver MISFET and the gate electrode of the second transfer MISFET are arranged in the first direction and such that a gate length direction thereof is in parallel with the first direction,
wherein the first driver MISFET and the second transfer MISFET are arranged in a second direction crossing to the first direction,
wherein the first transfer MISFET and the second drive MISFET are arranged in the second direction, and
wherein the load MISFETs are formed over the drive MISFETs and the transfer MISFETs with an insulating film interposed therebetween.
2. A semiconductor memory device according to claim 1 , wherein the gate electrode of the first drive MISFET is arranged, in the second direction, in aligned with the gate electrode of the second transfer MISFET, and
wherein the gate electrode of the first transfer MISFET is arranged, in the second direction, in aligned with the gate electrode of the second drive MISFET.
3. A semiconductor memory device according to claim 2 , wherein the first active region and the second active region are formed in a p well region,
wherein the transfer MISFETs and the drive MISFETs are n channel MISFETs, and
wherein the load MISFETs are p channel MISFETs.
4. A semiconductor memory device according to claim 2 , wherein the load MISFETs are vertical MISFETs.
5. A semiconductor memory device according to claim 1 , wherein the first active region and the second active region are formed in a p well region,
wherein the transfer MISFETs and the drive MISFETs are n channel MISFETs, and
wherein the load MISFETs are p channel MISFETs.
6. A semiconductor memory device according to claim 1 , wherein the load MISFETs are vertical MISFETs.
7. A semiconductor memory device comprising:
a memory cell with a first drive MISFET and a second drive MISFET, a first transfer MISFET and a second transfer MISFET and a first vertical MISFET and a second vertical MISFET,
wherein the drive MISFETs and the transfer MISFETs are formed on a major surface of a semiconductor substrate,
wherein a metal film is formed over the drive MISFETs and the transfer MISFETs with an insulating film interposed therebetween, and
wherein the vertical MISFETs are formed over the metal film,
wherein a barrier metal layer is formed over the metal film, and
wherein each of the vertical MISFETs is formed over the barrier metal film and is electrically connected to the metal film via the barrier metal film.
8. A semiconductor memory device according to claim 7 ,
wherein the barrier metal layer is comprised of a TiN film, and
wherein the metal layer is comprised of a W film.
9. A semiconductor memory device according to claim 7 ,
wherein each of the vertical MISFETs is electrically connected to the metal film via a throughhole such that the throughhole is formed inside of the barrier metal film.