Integrated circuit with high voltage junction structure
The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.
1. A high voltage integrated circuit comprising:
a P substrate;
a N well barrier in the substrate;
a control circuit, disposed outside the N well barrier;
a floating circuit, located inside the N well barrier; and
a high voltage barrier, formed for isolating the floating circuit from the control circuit when a predetermined high voltage is applied to the floating circuit, wherein, there is a distance between the floating circuit and the high voltage barrier, the distance is larger than 0 micro-meter.
2. The high voltage integrated circuit of claim 1 , further comprising P diffusion regions in the substrate for serving as isolation structures, wherein the P diffusion regions are disposed between the high voltage barrier and the floating circuit.
3. The high voltage integrated circuit of claim 1 , wherein a voltage supply to the floating circuit is fixed and a ground reference of the supply voltage is floated.
4. The high voltage integrated circuit of claim 1 , wherein the control circuit and the floating circuit include at least an N type MOSFET device comprising:
a first N diffusion region, forming a first N well in the substrate;
a first P diffusion region, forming a first P region in the first N well;
a first drain diffusion region, forming a first drain region in the first N diffusion region;
a first source diffusion region, forming a first source region, wherein a conduction channel is formed between the first source region and the first drain region; and
a first contact P diffusion region, forming a first contact P region, wherein the first P diffusion region encloses the first source region and the first contact P region.
5. The high voltage integrated circuit of claim 1 , wherein the control circuit and the floating circuit include at least a P type MOSFET device comprising:
a second N diffusion region, forming a second N well in the substrate;
a second P diffusion region, forming a second P region in the second N well;
a second drain diffusion region, forming a second drain region in the second P diffusion region;
a second source diffusion region, forming a second source region, wherein a conduction channel is formed between the second source region and the second drain region; and
a second contact N diffusion region, forming a second contact N region, wherein the second N diffusion region encloses the second source region and the second contact N region.
6. A high voltage integrated circuit, comprising:
a P substrate;
a N well barrier in the substrate;
a control circuit, disposed outside the N well barrier, comprising at least an N type MOSFET device and at least a P type MOSFET device;
a floating circuit, located inside the N well barrier, comprising at least an N type MOSFET device and at least a P type MOSFET device; and
a high voltage barrier, formed for isolating the floating circuit from the control circuit when a predetermined high voltage is applied to the floating circuit, wherein, there is a distance between the floating circuit and the high voltage barrier, the distance is larger than 0 micro-meter.
7. The high voltage integrated circuit of claim 1 , further comprising P diffusion regions in the substrate for serving as isolation structures, wherein the P diffusion regions are disposed between the high voltage barrier and the floating circuit.
8. The high voltage integrated circuit of claim 1 , wherein a voltage supply to the floating circuit is fixed and a ground reference of the supply voltage is floated.
9. The high voltage integrated circuit of claim 6 , wherein the N type MOSFET device comprises:
a first N diffusion region, forming a first N well in the substrate;
a first P diffusion region, forming a first P region in the first N well;
a first drain diffusion region, forming a first drain region in the first N diffusion region;
a first source diffusion region, forming a first source region, wherein a conduction channel is formed between the first source region and the first drain region; and
a first contact P diffusion region, forming a first contact P region, wherein the first P diffusion region encloses the first source region and the first contact P region.
10. The high voltage integrated circuit of claim 6 , wherein the P type MOSFET device comprises
a second N diffusion region, forming a second N well in the substrate;
a second P diffusion region, forming a second P region in the second N well;
a second drain diffusion region, forming a second drain region in the second P diffusion region;
a second source diffusion region, forming a second source region, wherein a conduction channel is formed between the second source region and the second drain region; and
a second contact N diffusion region, forming a second contact N region, wherein the second N diffusion region encloses the second source region and the second contact N region.
11. The high voltage integrated circuit of claim 6 , wherein a distance between the N type MOSFET device and the P type MOSFET device in the floating circuit is maintained sufficient to converge an electrical field when the predetermined high voltage is applied to the floating gate to generate the high voltage barrier for isolating the floating circuit from the control circuit.