Semiconductor integrated circuit device with a test circuit that measures a period to select a test mode
View Patent ↗A semiconductor integrated circuit device has a pair of oscillator terminals that is respectively provided with two oscillation signals having phases opposite to each other. An oscillator circuit provides an internal circuit with a system clock signal based on the oscillation signals. A mode detection circuit detects that the pair of oscillator terminals is respectively provided with two input signals having the same phase, and provides a test circuit with a detection signal. The test circuit sets a test mode according to the detection signal, and provides the internal circuit with a predetermined test signal. By setting the test mode using a pair of external terminals, an increase in the number of external terminals of the semiconductor integrated circuit device can be prevented.
1. A semiconductor integrated circuit device, comprising:
a pair of oscillator terminals;
an oscillator circuit for generating a clock signal that causes the semiconductor integrated circuit device to operate based on first and second oscillation signals with which the pair of oscillator terminals is provided respectively, the first and second oscillation signals having phases opposite to each other;
a detection circuit for generating a detection signal to set the semiconductor integrated circuit device in a test mode when the pair of oscillator terminals is provided with a first and second input signals having the same phase respectively; and
a test circuit, connected to the detection circuit, for measuring an output period during which the detection signal is being output from the detection circuit, and selecting one of a plurality of test modes based on a result of the measurement.
2. A semiconductor integrated circuit device, comprising:
a pair of oscillator terminals;
an oscillator circuit for generating a clock signal that causes the semiconductor integrated circuit device to operate based on first and second oscillation signals with which the pair of oscillator terminals is provided respectively, the first and second oscillation signals having phases opposite to each other;
a detection circuit for generating a detection signal to set the semiconductor integrated circuit device in a test mode when the pair of oscillator terminals is provided with a first and second input signals having the same phase respectively; and
a period determination circuit, connected to the detection circuit, for measuring a predetermined period, and supplying power to the detection circuit until the predetermined period elapses.
3. A semiconductor integrated circuit device, comprising:
a pair of oscillator terminals;
an oscillator circuit for generating a clock signal that causes the semiconductor integrated circuit device to operate based on first and second oscillation signals with which the pair of oscillator terminals is provided respectively, the first and second oscillation signals having phases opposite to each other;
a detection circuit for generating a detection signal to set the semiconductor integrated circuit device in a test mode when the pair of oscillator terminals is provided with a first and second input signals having the same phase respectively;
a period determination circuit, connected to the detection circuit, for measuring a predetermined period, and supplying power to the detection circuit until the predetermined period elapses; and
a register, connected to the period determination circuit, for setting the predetermined period.