IP Library Granted Patent US 7,282,434
Granted Patent B2
US 7,282,434 · App. 11/485,976 · Granted Oct 16, 2007

Method of manufacturing a semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,282,434
App. No.
11/485,976
Granted
Oct 16, 2007
Kind
B2
Abstract

A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

Claims (33)

1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate;

(b) forming a second insulating film comprising silicon oxide as a major component;

(c) forming a third insulating film comprising silicon carbide as a major component, wherein the third insulating film is in contact with both said first insulating film and said second insulating film;

(d) forming a fourth insulating film comprised of fluorine-containing silicon oxide;

(e) removing the fourth insulating film at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask; and

(f) forming first conductive layer buried inside the wiring groove and removing the first conductive layer from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

2. A method of manufacturing a semiconductor integrated circuit

device comprising the steps of:

(a) forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate;

(b) forming a second insulating film comprising silicon oxide as a major component;

(c) forming a third insulating film comprised of silicon carbide as a major component, wherein the third insulating film is in contact with both said first insulating film and said second insulating film;

(d) forming a fourth insulating film comprised of fluorine-containing silicon oxide

(e) removing the third and the fourth insulating films at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask; and

(f) forming first conductive layer buried inside the wiring groove and removing the first conductive layer from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

3. The method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein said first wiring is a conductive layer.

4. The method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein a first plug is formed in said first and said second insulating films and said first plug is integrally formed with said first wiring.

5. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said third insulating film is comprised of SiCN.

6. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said third insulating film is comprised of SiC.

7. The method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein said third insulating film is comprised of SiCN.

8. The method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein said third insulating film is comprised of SiC.

9. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein said second insulating film is comprised of SiON.

10. The method of manufacturing a semiconductor integrated circuit device according to claim 7 , wherein said second insulating film is comprised of SiON.

11. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:(a) forming a first interlayer insulating film including a first SiC film or a first SiCN film over a main surface of a semiconductor substrate;

(b) forming a first insulating film comprised of fluorine-containing silicon oxide;

(c) forming a second SiC film or a second SiCN film

(d) forming a second insulating film comprised of fluorine-containing silicon oxide;

(e) forming a third insulating film comprised of SiC, SiCN or silicon nitride, wherein the third insulating film is in contact with both said first insulating film and said second insulating film;

(f) removing the third insulating film at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask;

(g) removing the second insulating film, the second SiC film or the second SiCN film, and the first insulating film at part of the wiring groove-forming region by dry etching using a second photoresist film as a mask;

(h) removing the second insulating film at the wiring groove-forming region thereof by dry etching using the third insulating film as a mask;

(i) removing the third insulating film by dry etching and further removing the first SiC film by dry etching to form a first wiring groove in the first interlayer insulating film at the wiring groove-forming region thereof; and

(j) forming a first conductive layer buried inside the wiring groove and removing the first conductive layer from outside Of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the conductive layer inside wiring groove.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Jul 30, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025204/0512 →