Granted Patent B2

US 7,525,364 · App. 11/493,622 · Granted Apr 28, 2009

Abstract

Claims (46)

1. A delay control circuit, comprising:

a first variable delay circuit which delays an input signal to introduce a first delay into a first edge which is one of a rising edge and a falling edge of the input signal, thereby generates a first delay signal;

a second variable delay circuit which delays the input signal to introduce a second delay into a second edge which is the other one of the rising edge and the falling edge of the input signal, thereby generates a second delay signal;

a control circuit which generates a control signal for controlling the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical; and

a generation circuit which combines the first edge of the first delay signal and the second edge of the second delay signal, thereby generates a third delay signal,

wherein the generation circuit generates a rising edge of the third delay signal based on the first edge of the first delay signal and a falling edge of the third delay signal based on the second edge of the second delay signal, and the generation circuit includes a selection circuit for selecting the first edge of the first delay signal or the second edge of the second delay signal, and a latch circuit for latching the input signal by using the selected edge, and for generating the third delay signal.

2. The delay control circuit according to claim 1 , wherein:

the second variable delay circuit has a configuration equivalent to that of the first variable delay circuit; and

the control circuit outputs a control signal which is common to the first variable delay circuit and the second variable delay circuit.

3. The delay control circuit according to claim 2 , further comprising:

an inverter circuit which inverts the input signal, and which outputs the inverted signal, wherein:

the second variable delay circuit delays the inverted signal, and generates the second delay signal.

4. The delay control circuit according to claim 1 , wherein:

the first variable delay circuit and the second variable delay circuit respectively include a plurality of capacitor circuits, and a plurality of switch circuits for connecting the plurality of capacitor circuits to a transmission path of the input signal; and

the control circuit adjusts the first delay and the second delay by switching the plurality of switch circuits with the control signal.

5. The delay control circuit according to claim 1 , wherein:

the first variable delay circuit and the second variable delay circuit respectively include a capacitor circuit connected to a transmission path of the input signal, a plurality of current source circuits, and a plurality of switch circuits connecting the plurality of current source circuits to the transmission path; and

the control circuit adjusts the first delay and the second delay by switching the plurality of switch circuits with the control signal.

6. The delay control circuit according to claim 1 , wherein:

the first variable delay circuit and the second variable delay circuit respectively include a capacitor circuit connected to a transmission path of the input signal, a current source circuit, a switch circuit for connecting the current source circuit to the transmission path; and

the control circuit adjusts the first delay and the second delay by switching the switch circuit with the control signal and adjusting a time during which the current source circuit is connected to the transmission path.

7. A delay control circuit, comprising:

a first variable delay circuit which delays an input signal to introduce a first delay into a first edge which is one of a rising edge and a falling edge of the input signal, thereby generates a first delay signal;

a second variable delay circuit which delays the input signal to introduce a second delay into a second edge which is the other one of the rising edge and the falling edge of the input signal, thereby generates a second delay signal;

a control circuit which generates a control signal for controlling the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical; and

a generation circuit which combines the first edge of the first delay signal and the second edge of the second delay signal, thereby generates a third delay signal,

wherein the generation circuit generates a rising edge of the third delay signal based on the first edge of the first delay signal and a falling edge of the third delay signal based on the second edge of the second delay signal,

the first variable delay circuit delays the input signal, and generates a fourth delay signal; and

the control circuit includes a phase generation circuit for generating a phase comparison signal by using the fourth delay signal, and a phase detection circuit for detecting a phase difference by comparing phase relationships of the input signal and the phase comparison signal, and generates the control signal based on the detected phase difference.

8. The delay control circuit according to claim 7 , wherein:

the control circuit further includes a counter circuit for performing a count up operation or a count down operation based on the phase difference, and for outputting a count value, and generates the control signal from the count value.

9. The delay control circuit according to claim 7 , wherein:

the phase detection circuit includes a first comparison circuit for comparing the input signal and a threshold value signal by using an edge of the phase comparison signal, and a second comparison circuit for comparing the phase comparison signal and the threshold value signal by using an edge of the input signal.

10. A method of controlling a delay, comprising:

delaying an input signal to introduce a first delay into a first edge which is one of a rising edge and a falling edge of the input signal, thereby generating a first delay signal;

delaying the input signal to introduce a second delay into a second edge which is the other one of the rising edge and the falling edge of the input signal, thereby generating a second delay signal;

controlling the first delay and the second delay such that the first delay and the second delay are identical;

selecting the first edge of the first delay signal or the second edge of the second delay signal;

latching the input signal based on a selected edge in the selecting; and

combining the first edge of the first delay signal and the second edge of the second delay signal based on a latched input signal in the latching, thereby generating a third delay signal,

wherein the generating the third delay signal generates a rising edge of the third delay signal based on the first edge of the first delay signal and a falling edge of the third delay signal based on the second edge of the second delay signal.

11. A delay control circuit, comprising:

a first variable delay circuit which delays an input signal to introduce a first delay into a first edge which is one of a rising edge and a falling edge of the input signal, thereby generates a first delay signal;

a second variable delay circuit which delays the input signal to introduce a second delay into a second edge which is the other one of the rising edge and the falling edge of the input signal, thereby generates a second delay signal;

a control circuit which generates a control signal for controlling the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical; and

a generation circuit which combines the first edge of the first delay signal and the second edge of the second delay signal, thereby generates a third delay signal comprising a rising edge and a falling edge with an identical delay on the both edges from the both edges of the input signal.

Assignments (9)