Memory access control in a multiprocessor system
View Patent ↗Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t≡[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.
1. A method for controlling access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program, comprising:
granting access to the memory area to one of the first processor and the second processor at a time, where access to the memory area by the first processor and the second processor are cyclically uniquely allocated between the first and the second processor by the first and the second processor programs, where access to the memory allocated by the first and the second processor programs is furnished through cyclically uniquely allocated program addresses (ad),
where the step of granting comprises providing memory accesses to the memory area at the cyclically uniquely allocated program addresses (ad) for the first processor, which, in comparison with program addresses for memory accesses of the second processor are furnished at a value (o) offset relative to a cycle time (m).
2. A method for controlling access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program, comprising:
granting access to the memory area to one of the first processor and the second processor at a time, where access to the memory area by the first processor and the second processor are cyclically uniquely allocated between the first and the second processor by the first and second processor programs,
where the step of granting comprises providing memory accesses to the memory area at the cyclically uniquely allocated program addresses (ad) for the first processor, which, in comparison with program addresses for memory accesses of the second processor are furnished at a value (o) offset relative to a cycle time (m); and
where memory accesses of an o-th one of the processors occur at times and/or at processor program addresses ad satisfying the equality [(ad mod m)=o] where m is a value equal to or greater than the number of processors that cyclically uniquely access the memory area.
3. A method for controlling access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program, comprising:
granting access to the memory area to one of the first processor and the second processor at a time, where access to the memory area by the first processor and the second processor are cyclically uniquely allocated between the first and the second processor by the first and second processor programs,
where the step of granting comprises providing memory accesses to the memory area at the cyclically uniquely allocated program addresses (ad) for the first processor, which, in comparison with program addresses for memory accesses of the second processor are furnished at a value (o) offset relative to a cycle time (m); and
where the first and second processor programs execute temporally offset relative to one another and memory accesses within the first processor program are entered at program addresses (ad) cyclically equal relative to the second processor program.
4. A method for controlling access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program, comprising:
granting access to the memory area to one of the first processor and the second processor at a time, where access to the memory area by the first processor and the second processor are cyclically uniquely allocated between the first and the second processor by the first and second processor programs; and
where in the first processor program a program jump is entered from an instantaneous program address (ad) to a subsequent program address (ad new ) according to the cyclical allocation for the first processor; and
where a program jump satisfying [(ad new −1) mod m]=[ad mod m] is entered, where m is a value equal to or greater than the number of processors.