MOS transistor cell and semiconductor device
A MOS transistor cell having a salicide structure has a plurality of gate wires each formed as a straight line with a constant width. Each of the gate wires includes a P-channel gate terminal and an N-channel gate terminal. The P-side ends and the N-side ends of the gate wires are connected by means of respective two gate wire connecting portions at a boundary portion between the MOS transistor cell and another adjacent MOS transistor cell.
1 . A MOS transistor cell having a salicide structure, the MOS transistor cell comprising:
a plurality of gate wires each formed as a straight line with a constant width and comprising a P-channel gate terminal and an N-channel gate terminal.
2 . The MOS transistor cell of claim 1 , further comprising:
a gate wire connecting portion for connecting P-side ends of each of the plurality of gate wires; and
another gate wire connecting portion for connecting N-side ends of each of the plurality of gate wires.
3 . The MOS transistor cell of claim 2 , further comprising:
a gate electrode provided in a boundary portion with an adjacent MOS transistor cell and connected to the two gate wire connecting portions.
4 . The MOS transistor cell of claim 3 , further comprising:
a dummy gate electrode provided in a boundary portion with another adjacent MOS transistor cell in opposing relation to the gate electrode and unconnected to the two gate wire connecting portions,
wherein the gate electrode of the MOS transistor and a gate electrode of the adjacent MOS transistor are insulated from each other.
5 . The MOS transistor cell of claim 4 , wherein, when an MOS transistor cell is disposed adjacently to the dummy gate electrode, the dummy gate electrode is connected to the two gate wire connecting portions of the disposed MOS transistor cell and serves as the gate electrode thereof.
6 . A semiconductor device comprising:
the MOS transistor cell of claim 1; and
a dummy diffusion layer which does not compose a MOS transistor and is provided in a boundary portion with an adjacent MOS transistor cell.