Protection element and fabrication method for the same

1. A protection element of a semiconductor device formed on a semiconductor substrate,

the semiconductor device including:

the semiconductor substrate;

a gate insulating film formed on the semiconductor substrate; and

a word line formed on the gate insulating film,

the protection element comprising a MOS capacitor having:

the semiconductor substrate;

an insulating film formed on the semiconductor substrate and having a lower breakdown voltage than the gate insulating film; and

an extended portion of the word line formed on the insulating film, wherein:

a first well region having a conductivity type opposite to that of the semiconductor substrate is formed in a portion of the semiconductor substrate constituting the MOS capacitor, and

the insulating film is formed in contact with both a surface of the semiconductor substrate and a surface of the first well region.

2. The protection element of claim 1 , wherein when charge exceeding the breakdown voltage of the insulating film constituting the MOS capacitor is induced in the word line and the extended portion of the word line, the induced charge is released into either the semiconductor substrate or the first well region depending on whether the induced charge is positive or negative.

3. The protection element of claim 1 , wherein the semiconductor device is a nonvolatile semiconductor memory device having MONOS memory cells,

the word line is a word line of the MONOS memory cell, and

the extended portion of the word line is a word line extending from the MONOS memory cells.

4. The protection element of claim 1 , wherein a first high-density impurity diffusion layer having the same conductivity type as the first well region is formed on the first well region,

the first high-density impurity diffusion layer partly extends on the surface of the semiconductor substrate adjacent to the first well region, and

the insulating film is formed in contact with both the surface of the semiconductor substrate and a surface of the first high-density impurity diffusion layer.

5. The protection element of claim 4 , wherein a second high-density impurity diffusion layer having the same conductivity type as the semiconductor substrate is formed on the surface of the semiconductor substrate,

the second high-density impurity diffusion layer is adjacent to the first high-density impurity diffusion layer, and

the insulating film is formed in contact with both the surface of the first high-density impurity diffusion layer and a surface of the second high-density impurity diffusion layer.

6. The protection element of claim 1 , wherein

a conductive layer is formed in contact with the surface of the first well region and the surface of

the semiconductor substrate adjacent to the first well region.

7. The protection element of claim 3 , wherein the breakdown voltage of the insulating film constituting the MOS capacitor is smaller than breakdown voltage of an ONO film constituting a gate insulating film of the MONOS memory cells.

8. The protection element of claim 1 , wherein a second well region having the same conductivity type as the semiconductor substrate is formed in a portion of the semiconductor substrate constituting the MOS capacitor next to the first well region, and

the insulating film is formed in contact with both the surface of the first well region and a surface of the second well region.

9. The protection element of claim 8 , wherein a third well region having a conductivity type opposite to that of the semiconductor substrate is formed in a portion of the semiconductor substrate, and

the first well region and the second well region are located in the third well region.