Circuit for detecting difference in capacitance
View Patent ↗A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor includes an oscillator configured to generate an oscillating signal, a phase comparator coupled to the oscillator to output a signal responsive to a phase difference between the oscillating signal delayed by the first capacitor and the oscillating signal delayed by the second capacitor, an integration circuit coupled to the phase comparator to output an integrated signal made by integrating the signal responsive to the phase difference over a time period equal to a predetermined number of cycles of the oscillating signal, and a sample-and-hold circuit coupled to the integration circuit to output a signal made by sampling and holding the integrated signal at substantially an end of the time period.
1. A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor, comprising:
a first oscillator configured to generate a first oscillating signal having frequency responsive to the first capacitor;
a second oscillator configured to generate a second oscillating signal having frequency responsive to the second capacitor;
a first counter coupled to said first oscillator to output a first count responsive to said first oscillating signal;
a second counter coupled to said second oscillator to output a second count responsive to said second oscillating signal;
an oscillation circuit configured to generate a drive signal for driving the sensor to cause harmonic motion to the first capacitor and the second capacitor;
a control circuit configured to output a timing signal indicative of directions of the harmonic motion in response to the drive signal; and
an operation circuit coupled to said first counter, said second counter, and said control circuit to obtain an annular rate applied to the sensor in response to the first count, the second count, and the timing signal.
2. The circuit as claimed in claim 1 , further comprising:
a first frequency amplifier circuit coupled to said first oscillator to output a third oscillating signal having frequency equal to a multiple of the frequency of the first oscillating signal; and
a second frequency amplifier circuit coupled to said second oscillator to output a fourth oscillating signal having frequency equal to a multiple of the frequency of the second oscillating signal,
wherein said first counter is coupled to said first frequency amplifier circuit to count the third oscillating signal to output the first count, and said second counter is coupled to said second frequency amplifier circuit to count the fourth oscillating signal to output the second count.
3. The circuit as claimed in claim 1 , further comprising a synchronizing circuit configured to synchronize said first and second oscillators with the drive signal while allowing for changes in the first and second oscillating signals responsive to changes in the first and second capacitors.
4. The circuit as claimed in claim 3 , wherein said synchronizing circuit is a PLL circuit including a low-pass filter, said low-pass filter having frequency-band characteristics that block frequencies corresponding to the first and second oscillating signals and that allow passage of frequencies corresponding to changes in the first and second oscillating signals.
5. The circuit as claimed in claim 3 , wherein said synchronizing circuit includes VCOs, said first and second oscillators being said VCOs.